Searched refs:well (Results 201 – 225 of 401) sorted by relevance
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| /Zephyr-latest/boards/st/nucleo_h743zi/doc/ |
| D | index.rst | 111 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/doc/kernel/object_cores/ |
| D | index.rst | 54 object core statistics as well as the structures used for both "raw" and
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| /Zephyr-latest/boards/adi/eval_adin2111ebz/doc/ |
| D | index.rst | 108 EVAL-ADIN2111EBZ System Clock could be driven by an internal or external oscillator, as well as the
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| /Zephyr-latest/samples/kernel/metairq_dispatch/ |
| D | README.rst | 55 This sample should run well on any Zephyr platform that provides
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| /Zephyr-latest/boards/st/nucleo_l432kc/doc/ |
| D | index.rst | 126 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
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| /Zephyr-latest/boards/st/nucleo_l433rc_p/doc/ |
| D | index.rst | 129 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
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| /Zephyr-latest/doc/build/dts/ |
| D | phandles.rst | 178 Such properties can contain multiple values as well:
231 you can create your own as well.
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| /Zephyr-latest/subsys/llext/ |
| D | Kconfig | 170 portable option, but it may not compress as well as XZ or Zstd.
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| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 79 as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock
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| /Zephyr-latest/boards/lilygo/ttgo_lora32/doc/ |
| D | index.rst | 36 | USB Port | USB interface. Power supply for the board as well as the |
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| /Zephyr-latest/boards/weact/mini_stm32h743/doc/ |
| D | index.rst | 101 as well as by the main PLL clock. By default, the System clock is driven
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| /Zephyr-latest/boards/m5stack/m5stickc_plus/doc/ |
| D | index.rst | 42 | USB Port | USB interface. Power supply for the board as well as the |
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| /Zephyr-latest/boards/st/stm32f7508_dk/doc/ |
| D | index.rst | 123 as well as by the main PLL clock. By default, the System clock is driven by the PLL
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| /Zephyr-latest/boards/st/stm32l476g_disco/doc/ |
| D | index.rst | 125 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
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| /Zephyr-latest/boards/st/stm32f769i_disco/doc/ |
| D | index.rst | 118 as well as by the main PLL clock. By default, the System clock is driven by the PLL
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| /Zephyr-latest/doc/connectivity/networking/api/ |
| D | coap_server.rst | 283 ``.well-known/core`` GET requests by the server. This allows clients to get a list of hypermedia
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| /Zephyr-latest/doc/connectivity/bluetooth/api/mesh/ |
| D | core.rst | 105 outgoing messages, as well as other work items submitted to the system
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| D | dfu_srv.rst | 85 about which image is being updated, as well as the update metadata.
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| /Zephyr-latest/boards/st/stm32f746g_disco/doc/ |
| D | index.rst | 128 as well as by the main PLL clock. By default, the System clock is driven by the PLL
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| /Zephyr-latest/doc/kernel/services/synchronization/ |
| D | mutexes.rst | 84 This works well for priority inheritance as long as only one locked mutex is
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| /Zephyr-latest/boards/m5stack/m5stack_core2/doc/ |
| D | index.rst | 55 | USB Port | USB interface. Power supply for the board as well as the | sup…
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| /Zephyr-latest/boards/st/sensortile_box/doc/ |
| D | index.rst | 97 oscillator, as well as main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/st/nucleo_g474re/doc/ |
| D | index.rst | 137 as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz,
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| /Zephyr-latest/boards/st/nucleo_g431rb/doc/ |
| D | index.rst | 133 as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz,
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| /Zephyr-latest/boards/st/nucleo_l496zg/doc/ |
| D | index.rst | 136 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
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