| /Zephyr-latest/arch/x86/include/ |
| D | kernel_arch_func.h | 51 FUNC_NORETURN void z_x86_unhandled_cpu_exception(uintptr_t vector,
107 uint8_t vector,
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.intel_vtd | 15 multi-vector support. If you have such PCIe device requiring
16 multi-vector support, you will need to enable this.
36 other device that would require it for MSI/MSI-X multi-vector support.
|
| D | intc_intel_vtd.c | 337 msi_vector_t *vector, in vtd_ictl_remap_msi() argument
342 return VTD_MSI_MAP(vector->arch.irte, shv); in vtd_ictl_remap_msi()
347 uint16_t vector, in vtd_ictl_remap() argument
355 irte.bits.vector = vector; in vtd_ictl_remap()
395 uint16_t vector) in vtd_ictl_set_irte_vector() argument
399 data->vectors[irte_idx] = vector; in vtd_ictl_set_irte_vector()
405 uint16_t vector) in vtd_ictl_get_irte_by_vector() argument
411 if (data->vectors[irte_idx] == vector) { in vtd_ictl_get_irte_by_vector()
|
| /Zephyr-latest/subsys/testsuite/include/zephyr/ |
| D | interrupt_util.h | 135 static inline void trigger_irq(int vector) in trigger_irq() argument
140 x86_write_x2apic(LOAPIC_SELF_IPI, ((VECTOR_MASK & vector))); in trigger_irq()
148 z_loapic_ipi(cpu_id, LOAPIC_ICR_IPI_TEST, vector); in trigger_irq()
|
| /Zephyr-latest/scripts/coredump/gdbstubs/arch/ |
| D | x86.py | 122 vector = self.exception_vector
124 if vector is None:
128 if vector in self.GDB_SIGNAL_MAPPING:
129 sig = self.GDB_SIGNAL_MAPPING[vector]
|
| D | x86_64.py | 161 vector = self.exception_vector
163 if vector is None:
167 if vector in self.GDB_SIGNAL_MAPPING:
168 sig = self.GDB_SIGNAL_MAPPING[vector]
|
| /Zephyr-latest/arch/arm/core/ |
| D | vector_table.ld | 17 * of the vector table is 64-word aligned.
22 * of the vector table is 32-word aligned.
30 * exception entries in the vector table. The minimum alignment of 32 words
43 * For AArch32 (M), VTOR has Bits [6:0] = RES0. Thus, vector start address
|
| /Zephyr-latest/arch/arm/ |
| D | Kconfig | 41 Relocates the rom_start region containing the boot-vector data and
46 such that it is able to load the correct boot-vector (contained in rom_start)
50 Most SOCs include an alias for the boot-vector at address 0x00000000
55 is not placed into the boot-vector memory area.
63 for code location. But the boot-vector must be placed into OCRAM_S for the
76 to the right memory region of the boot-vector.
79 -IMX7D the boot-vector is OCRAM_S (0x00180000, aliased at 0x0).
80 -IMX6SX the boot-vector is TCML (0x007F8000, aliased at 0x0).
81 -IMX8MQ the boot-vector is TCML (0x007E0000, aliased at 0x0).
82 -IMX8MN the boot-vector is ITCM (0x007E0000, aliased at 0x0).
[all …]
|
| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | CMakeLists.txt | 8 vector.S
|
| /Zephyr-latest/arch/x86/core/intel64/ |
| D | coredump.c | 14 uint64_t vector; member
65 arch_blk.vector = esf->vector; in arch_coredump_info_dump()
|
| D | cpu.c | 54 uint8_t vector = ((unsigned long) x86_ap_start) >> 12; in arch_cpu_start() local
82 z_loapic_ipi(apic_id, LOAPIC_ICR_IPI_STARTUP, vector); in arch_cpu_start()
|
| /Zephyr-latest/tests/arch/arm/arm_irq_vector_table/ |
| D | README.txt | 5 Verify a project can install ISRs directly in the vector table. Only for
34 tc_start() - Test Cortex-M3 IRQ installed directly in vector table
|
| D | CMakeLists.txt | 11 zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors irq-vector-table.ld)
|
| /Zephyr-latest/soc/ite/ec/common/ |
| D | CMakeLists.txt | 7 vector.S
|
| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | sysapic.h | 23 void z_irq_controller_irq_config(unsigned int vector, unsigned int irq,
|
| /Zephyr-latest/drivers/sensor/nxp/fxos8700/ |
| D | Kconfig | 111 bool "Magnetic vector-magnitude detection"
113 Enable magnetic vector-magnitude detection
118 bool "Magnetic vector-magnitude interrupt to INT1 pin"
120 Say Y to route magnetic vector-magnitude interrupt to INT1 pin.
|
| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | vt_pointer_section.ld | 7 /* Reserved 4 bytes to save vector table base address */
|
| D | relay_vector_table.ld | 16 * of the vector table is 32-word aligned.
21 * exception entries in the vector table. The minimum alignment of 32 words
|
| D | CMakeLists.txt | 44 # Using 0x0 prefix will result in placing the relay vector table section
46 # required for CPUs without VTOR, which need to have the exception vector
|
| /Zephyr-latest/soc/wch/ch32v00x/ |
| D | CMakeLists.txt | 6 vector.S
|
| /Zephyr-latest/arch/arc/core/ |
| D | vector_table.ld | 7 /* when !XIP, .text is in RAM, and vector table must be at its very start */
|
| /Zephyr-latest/arch/sparc/ |
| D | Kconfig | 30 bool "Single-vector trapping"
32 Use Single-vector trapping (SVT). Defined by SPARC-V8 Embedded (V8E)
|
| /Zephyr-latest/arch/x86/core/ia32/ |
| D | gdbstub.c | 20 static unsigned int get_exception(unsigned int vector) in get_exception() argument
24 switch (vector) { in get_exception()
81 static void z_gdb_interrupt(unsigned int vector, struct arch_esf *esf) in z_gdb_interrupt() argument
83 debug_ctx.exception = get_exception(vector); in z_gdb_interrupt()
|
| D | irq_offload.c | 46 [vector] "i" (CONFIG_IRQ_OFFLOAD_VECTOR)); in arch_irq_offload()
|
| /Zephyr-latest/soc/qemu/malta/ |
| D | CMakeLists.txt | 11 vector.S
|
