Searched refs:riscv (Results 26 – 50 of 117) sorted by relevance
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| /Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/ |
| D | alt_mapping.overlay | 10 riscv,max-priority = <7>;
11 riscv,ndev = < 1024 >;
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv32-fe310.dtsi | 30 compatible = "sifive,e31", "riscv";
33 riscv,isa = "rv32imac_zicsr_zifencei";
36 compatible = "riscv,cpu-intc";
69 compatible = "riscv,machine-timer";
75 compatible = "sifive,debug-013", "riscv,debug-013";
133 riscv,max-priority = <7>;
134 riscv,ndev = <52>;
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| /Zephyr-latest/boards/microchip/m2gl025_miv/doc/ |
| D | index.rst | 41 <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
53 <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
56 -ex "set arch riscv:rv32" \
57 -ex "set riscv use_compressed_breakpoints no" \
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| /Zephyr-latest/dts/riscv/telink/ |
| D | telink_b91.dtsi | 25 compatible ="telink,b91", "riscv";
26 riscv,isa = "rv32imac_zicsr_zifencei";
28 compatible = "riscv,cpu-intc";
51 compatible = "riscv,machine-timer";
136 riscv,max-priority = <3>;
137 riscv,ndev = <63>;
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| /Zephyr-latest/boards/microchip/mpfs_icicle/doc/ |
| D | index.rst | 46 <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
58 <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
61 -ex "set arch riscv:rv64" \
62 -ex "set riscv use_compressed_breakpoints no" \
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| /Zephyr-latest/soc/common/ |
| D | CMakeLists.txt | 4 add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged)
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| D | Kconfig | 6 rsource "riscv-privileged/Kconfig"
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| /Zephyr-latest/boards/sifive/hifive1/support/ |
| D | openocd.cfg | 9 set _CHIPNAME riscv
13 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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| /Zephyr-latest/soc/microchip/miv/polarfire/ |
| D | CMakeLists.txt | 5 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/starfive/jh71xx/ |
| D | CMakeLists.txt | 5 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/renode/riscv_virtual/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/efinix/sapphire/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/intel/intel_niosv/niosv/ |
| D | linker.ld | 8 #include <zephyr/arch/riscv/common/linker.ld>
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| /Zephyr-latest/dts/riscv/ |
| D | neorv32.dtsi | 22 compatible = "neorv32,cpu", "riscv";
27 compatible = "riscv,cpu-intc";
90 compatible = "riscv,machine-timer";
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| /Zephyr-latest/soc/wch/ch32v/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/microchip/miv/miv/ |
| D | CMakeLists.txt | 6 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/qemu/virt_riscv/ |
| D | CMakeLists.txt | 4 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/lowrisc/opentitan/ |
| D | CMakeLists.txt | 7 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/arch/riscv/ |
| D | CMakeLists.txt | 5 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/arch/riscv/error.h)
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| /Zephyr-latest/soc/neorv32/ |
| D | CMakeLists.txt | 10 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/soc/nordic/common/vpr/ |
| D | CMakeLists.txt | 9 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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| /Zephyr-latest/doc/hardware/arch/ |
| D | semihost.rst | 68 .. _RISC-V Github documentation: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-se…
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