Searched refs:level (Results 326 – 350 of 843) sorted by relevance
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42 USB host thread initialization priority level.
56 uint32_t level : LOG_FRONTEND_STMESP_DEMUX_LEVEL_BITS; member
5 for sensors on a per device level. Each device must specify a device tree binding
94 uint16_t level_to_light_ctl_temp(int16_t level) in level_to_light_ctl_temp() argument103 tmp = (uint16_t) ((level - INT16_MIN) * diff); in level_to_light_ctl_temp()
47 Priority level of the internal CANopen transmit workqueue.101 Priority level of the internal thread which processes
36 # That's why in the top level of SoC definitions (for user-configurable
61 logging.basicConfig(level='DEBUG')
21 yet been completed. This allows for testing that high-level code can
25 module-str = Log level for IP-to-IP tunnel
16 listen :<dir=tx,rx,txrx> [security level]
35 Priority level for the internal ADC data acquisition thread.
30 module-str = Log level for zperf
39 module-str = Log level for packet filtering
137 level = next((lvl for lvl in self.levels if lvl.name == name), None)138 return level150 for level in levels:152 for s in level.get('adds', []):157 tl.name = level['name']159 tl.levels = level.get('inherits', [])163 for level in levels:164 inherit = level.get('inherits', [])165 _level = self.get_level(level['name'])849 if self.options.level:[all …]
325 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level) in flash_stm32_set_rdp_level() argument328 (uint32_t)level << FLASH_OPTR_RDP_Pos); in flash_stm32_set_rdp_level()
746 int level = 1, count = 0, i; in cad_qspi_read_bank() local761 level = CAD_QSPI_SRAMFILL_INDRDPART( in cad_qspi_read_bank()764 for (i = 0; i < level; ++i) { in cad_qspi_read_bank()768 read_count += level * sizeof(uint32_t); in cad_qspi_read_bank()770 } while (level > 0); in cad_qspi_read_bank()
170 high-level;171 low-level;
32 Security changed: XX:XX:XX:XX:XX:XX level 281 Security changed: XX:XX:XX:XX:XX:XX level 2
14 module-str = Log level for Ethernet PHY driver15 module-help = Sets log level for Ethernet PHY Device Drivers.
126 interrupt priority level, in all Cortex-M variants. The main reasons for that design are221 By design, system fault exceptions have the highest priority level. In227 UsageFault, etc.) are assigned the highest *configurable* priority level.231 This priority level is never shared with HW interrupts (an exception to236 SVC exception is normally configured with the highest configurable priority level241 In Baseline Cortex-M the priority level of SVC may be shared with other exceptions242 or HW interrupts that are also given the highest configurable priority level (As a247 In Mainline Cortex-M, however, the SVC priority level is *reserved*, thus normally it253 HW interrupts in Mainline Cortex-M builds are allocated a priority level lower than the SVC.256 (ZLIs). Such interrupts are designed to have a priority level higher than any HW or system[all …]
343 static void security_changed(struct bt_conn *conn, bt_security_t level, enum bt_security_err err) in security_changed() argument350 LOG_DBG("Security changed: %s level %u", addr, level); in security_changed()352 LOG_DBG("Security failed: %s level %u err %d %s", addr, level, in security_changed()
194 static void security_changed(struct bt_conn *conn, bt_security_t level, enum bt_security_err err) in security_changed() argument201 LOG_ERR("Security for %p failed: %s level %u err %d", conn, addr, level, err); in security_changed()205 LOG_INF("Security for %p changed: %s level %u", conn, addr, level); in security_changed()
505 data_ptr, cfg_ptr, level, prio, \ argument514 data_ptr, cfg_ptr, level, prio, \531 data_ptr, cfg_ptr, level, prio, \ argument534 data_ptr, cfg_ptr, level, prio, \
18 or keys defined at the board level that can generate input events.
12 …e coexistence ticker utilizes a single pin called BLE_GRANT, which active level (high or low) is p…
