Searched refs:flash (Results 226 – 250 of 2906) sorted by relevance
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12 the flash memory beginning address. This rule shall be applied to13 all flash controller regular memory that layout is accessible via16 An exception from the rule may be applied to a vendor-specific flash
13 - 256 KiB flash memory and 32 KiB of RAM31 A debug adapter is required to flash and debug programs.43 You can build and flash with ``west flash`` command (See52 :goals: build flash57 :goals: build flash100 pyocd flash -e sector -a 0x0 -t r7fa4m1ab dfu_minima.hex105 pyocd flash -e sector -a 0x0 -t r7fa4m1ab dfu_wifi.hex
11 flash-controller@52002000 {12 flash0: flash@8000000 {
15 flash-controller@40022000 {16 flash0: flash@8000000 {
16 flash-controller@40022000 {17 flash0: flash@8000000 {
4 bool "Nios-II QSPI flash driver"11 Enables the Nios-II QSPI flash driver.
5 bool "Telink Semiconductor B91 flash driver"12 Enables Telink B91 flash driver.
5 bool "ADI MAX32 flash driver"12 Enable MAX32 internal flash driver.
20 flash-controller@40022000 {21 flash0: flash@8000000 {
28 :goals: build flash51 OTP Fuse setting to wake from Deep Power Down and reset flash59 flash is not normally reset when waking from DPD. This sample60 eXecutes-In-Place (XIP) from the external flash. When the MCU wakes from61 DPD, it wakes through the reset flow. But if the external flash is not62 reset, the MCU and flash are no longer in sync, and the MCU cannot XIP.67 able to XIP from the flash to resume. One can press the Reset button in70 To wake from DPD and resume XIP from the flash, the MCU needs to be71 configured to reset the external flash. This can be done by programming73 how program the OTP BOOT_CFG1 fuses to use GPIO pin PIO4_5 as the flash[all …]
16 flash-controller@400a0000 {17 flash0: flash@0 {
12 flash-controller@400e0a00 {13 flash0: flash@400000 {
17 rmc: flash-controller@4000c000 {18 flash0: flash@0 {
