Searched refs:domain (Results 251 – 275 of 283) sorted by relevance
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xec_qmspi_ldma.c | 1032 DT_INST_CLOCKS_CELL(i, domain))
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| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig | 274 FPU usage or security domain.
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| /Zephyr-latest/subsys/net/lib/dns/ |
| D | Kconfig | 51 Defines the max number of IP addresses per domain name
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| D | mdns_responder.c | 551 record->proto, record->domain, in send_sd_response()
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| /Zephyr-latest/arch/ |
| D | Kconfig | 269 (Normal) domain.
280 interrupts etc.) belonging to the Secure domain.
904 regions available for application memory domain programming.
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| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | controller.rst | 16 CAN is mostly known for its application in the automotive domain. However, it
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| /Zephyr-latest/samples/net/mqtt_publisher/ |
| D | README.rst | 217 Common Name (CN) in the certificate file in order for the TLS domain
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-4.0.rst | 758 * STM32: HSE can now be used as domain clock.
912 * Add regulatory domain support to Wi-Fi shell.
1207 * Renamed ``power-domain`` base property to ``power-domains``,
1208 and introduced ``power-domain-names`` property. ``#power-domain-cells`` is now required as well.
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| D | release-notes-2.5.rst | 357 (SPE) when building Zephyr for the non-secure domain.
1509 * :github:`29382` - remove memory domain restriction on system RAM for memory partitions on MMU dev…
1726 * :github:`27785` - memory domain arch implementation not correct with respect to SMP on ARC
1864 * :github:`21991` - memory domain locking may not be entirely correct
1907 * :github:`17545` - Licensing and reference to public domain material
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| D | release-notes-1.11.rst | 446 * :github:`5992` - doc: Discrepancy in Zephyr memory domain API documentation
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| D | migration-guide-3.6.rst | 280 domain/kernel clock via devicetree. Previously, the driver only supported using the PLL1_Q clock
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| D | release-notes-3.2.rst | 151 * STM32 LPTIM domain clock should now be configured using devicetree.
260 might cause Cortex-A57 to incorrectly trigger a domain fault".
525 * STM32: PLL_P, PLL_Q, PLL_R outputs can now be used as domain clock.
1100 * :dtcompatible:`intel,adsp-power-domain`
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| D | release-notes-2.4.rst | 199 * All threads now are always a member of a memory domain. A new
200 memory domain ``k_mem_domain_default`` introduced for initial threads
1096 * :github:`27785` - memory domain arch implementation not correct with respect to SMP on ARC
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| D | release-notes-3.3.rst | 576 and configured as domain clock for these devices, otherwise PLL_Q output or MSI is used.
657 * STM32 RTC based counter domain clock (LSE/SLI) should now be configured using device tree.
1157 * Added support for regulatory domain configuration.
1583 - :dtcompatible:`intel,adsp-power-domain`:
1692 - new property: ``power-domain``
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| D | release-notes-1.14.rst | 577 - The build time memory domain partition generation mechanism, formerly
623 * Indicate Secure domain fault in Non-Secure fault exception
1154 * :github:`15178` - samples/mpu/mem_domain_apis_test: Did not get to "destroy app0 domain", went i…
1407 * :github:`13918` - x86 memory domain configuration not always applied correctly on context switch …
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| /Zephyr-latest/doc/develop/debug/ |
| D | index.rst | 91 device. GDB releases 9.0 and newer also support Unix domain sockets.
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| /Zephyr-latest/arch/x86/ |
| D | Kconfig | 342 default memory domain. Instantiation of additional memory domains
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| /Zephyr-latest/subsys/net/lib/sockets/ |
| D | Kconfig | 328 Communicate over a pair of connected, unnamed UNIX domain sockets.
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| /Zephyr-latest/dts/arm/st/u5/ |
| D | stm32u5.dtsi | 745 * The SDMMC domain clock can be chosen between ICLK and PLL1P.
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| /Zephyr-latest/boards/espressif/esp_wrover_kit/doc/ |
| D | index.rst | 516 Zephyr build. Output is structured by the domain subdirectories:
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| /Zephyr-latest/boards/espressif/esp32_ethernet_kit/doc/ |
| D | index.rst | 485 Zephyr build. Output is structured by the domain subdirectories:
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| /Zephyr-latest/doc/hardware/porting/ |
| D | arch.rst | 806 number of regions for a memory domain. MMU systems have an unlimited amount,
810 or modify hardware registers on another CPU when memory domain APIs are invoked.
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| /Zephyr-latest/doc/build/dts/ |
| D | bindings-syntax.rst | 56 # "Specifier" cell names for the 'foo' domain go here; example 'foo'
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| /Zephyr-latest/doc/hardware/arch/ |
| D | arm_cortex_m.rst | 501 domain.
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| /Zephyr-latest/kernel/ |
| D | Kconfig | 866 source frequency domain multiplied by target frequency fits in 64 bits.
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