Searched refs:default (Results 401 – 425 of 5614) sorted by relevance
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10 default ""18 default "000102030405060708090a0b0c0d0e0f"25 default 132 default "coap://leshan.eclipseprojects.io:5683" if (WIFI && !LWM2M_DTLS_SUPPORT)33 default "coaps://leshan.eclipseprojects.io:5684" if (WIFI && LWM2M_DTLS_SUPPORT)34 default "coap://192.0.2.2:5683" if !LWM2M_DTLS_SUPPORT35 default "coaps://192.0.2.2:5684" if (LWM2M_DTLS_SUPPORT && !LWM2M_RD_CLIENT_SUPPORT_BOOTSTRAP)36 default "coaps://192.0.2.2:5784" if (LWM2M_DTLS_SUPPORT && LWM2M_RD_CLIENT_SUPPORT_BOOTSTRAP)
9 default y15 default 1022 default y28 default 435 default y41 default 448 default y54 default 4
63 pinctrl-names = "default";70 pinctrl-names = "default";76 pinctrl-names = "default";82 pinctrl-names = "default";90 pinctrl-names = "default";97 pinctrl-names = "default";112 pinctrl-names = "default";118 pinctrl-names = "default";130 pinctrl-names = "default";
7 default 49610 default 100013 default 13 if SOC_NRF9230_ENGB17 default n
9 default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk"10 default "nrf5340bsim/nrf5340/cpunet" if $(BOARD) = "nrf5340bsim"11 default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"12 default "stm32h747i_disco/stm32h747xx/m4" if $(BOARD) = "stm32h747i_disco"
11 default y16 default 1619 default LV_COLOR_DEPTH_16 # 16 bit per pixel23 default y
9 default y12 default y if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M315 default 718 default y if "$(dt_nodelabel_enabled,daplink_qspi_mux)"
8 # Use External Memory Configuration Data (XMCD) by default when booting primary core (M33)10 default y if CPU_CORTEX_M3313 default y if CPU_CORTEX_M3316 default y
36 default "cc13x2x7_cc26x2x7" if SOC_SERIES_CC13X2X7_CC26X2X739 default "cc1352p7" if SOC_CC1352P740 default "cc1352r7" if SOC_CC1352R741 default "cc2652p7" if SOC_CC2652P742 default "cc2652r7" if SOC_CC2652R7
37 default "cc13x2_cc26x2" if SOC_SERIES_CC13X2_CC26X240 default "cc1352p" if SOC_CC1352P41 default "cc1352r" if SOC_CC1352R42 default "cc2652p" if SOC_CC2652P43 default "cc2652r" if SOC_CC2652R
16 default y26 default y34 default y56 default 7560 default y69 default y86 default y96 default y106 default y120 default y[all …]
10 default 17813 default 8000000016 default 0x800 if XIP17 default 0x0 if !XIP
10 default 17913 default 8000000016 default 0x800 if XIP17 default 0x0 if !XIP
18 default y35 default y42 default y48 default y65 default y72 default y79 default y86 default y93 default y100 default y[all …]
16 default 1524 the default value works fine with them.38 default 7 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_739 default 6 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_640 default 5 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_541 default 4 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_442 default 3 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_343 default 2 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_244 default 1 if MCUMGR_SMP_CBOR_MIN_DECODING_LEVEL_145 default 0[all …]
143 default y151 default y166 default y184 default y200 default ""213 default 16223 default 1231 default 6 if BT_HCI_RAW232 default 1242 default 8[all …]
25 default 3034 default 447 default y56 default 475 default 0x0082 default 0x0089 default 0x5e96 default 0x00103 default 0x53110 default 0x8d[all …]
5 # Infineon PSOC 6_01 based MCU default configuration10 default 32 if CPU_CORTEX_M0PLUS11 default 147 if CPU_CORTEX_M414 default 100000000
5 # Infineon PSOC 6_03 based MCU default configuration10 default 16 if CPU_CORTEX_M0PLUS11 default 174 if CPU_CORTEX_M414 default 100000000
5 # Infineon PSOC 6_04 based MCU default configuration10 default 16 if CPU_CORTEX_M0PLUS11 default 175 if CPU_CORTEX_M414 default 100000000
5 # Infineon PSOC 6 (Legacy) based MCU default configuration10 default 32 if CPU_CORTEX_M0PLUS11 default 147 if CPU_CORTEX_M414 default 50000000
11 default 0x9A14 default 117 default y25 default y
