Searched refs:core (Results 426 – 450 of 877) sorted by relevance
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| /Zephyr-latest/doc/hardware/cache/ |
| D | guide.rst | 27 When dealing with memory shared between a processor core and other bus masters,
29 close to each processor core as possible to maximize performance gain. Because
36 core and peripherals is coherent. The simplest is just to disable caching, but
146 caching in which data writes from the processor core propagate through to
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | intel_adsp.py | 17 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| D | spi_burn.py | 10 from runners.core import BuildConfiguration, RunnerCaps, ZephyrBinaryRunner
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| /Zephyr-latest/dts/xtensa/nxp/ |
| D | nxp_imx8ulp.dtsi | 26 compatible = "cdns,xtensa-core-intc";
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| /Zephyr-latest/boards/arduino/opta/ |
| D | arduino_opta_stm32h747xx_m7.dts | 15 model = "Arduino OPTA M7 core Programmable Logic Controller";
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| /Zephyr-latest/boards/efinix/titanium_ti60_f225/doc/ |
| D | index.rst | 8 which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set an…
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| /Zephyr-latest/boards/nuvoton/numaker_pfm_m467/ |
| D | numaker_pfm_m467.dts | 68 core-clock = <192000000>;
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | Kconfig.defconfig | 1 # RV32M1 SoC RISC-V core default configuration values
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| /Zephyr-latest/samples/boards/nxp/mimxrt1060_evk/system_off/ |
| D | README.rst | 45 MIMXRT1060_EVK core output
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| /Zephyr-latest/samples/boards/st/power_mgmt/suspend_to_ram/ |
| D | README.rst | 23 in core sleep states, as LPTIM (:dtcompatible:`st,stm32-lptim`).
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| /Zephyr-latest/samples/bluetooth/hci_ipc/ |
| D | README.rst | 33 Zephyr's Bluetooth :ref:`bt_hci_drivers` core. See the
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| /Zephyr-latest/scripts/west_commands/ |
| D | patch.py | 16 import pykwalify.core
312 return pykwalify.core.Core(source_data={}, schema_data=patches_schema).validate()
317 return pykwalify.core.Core(source_data=yml, schema_data=patches_schema).validate()
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | Kconfig | 9 # NOTE: We have the specific core implementations first and outside of the
11 # select which core they are using without having to select all the options
12 # related to that core. Everything else is captured inside the if
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| /Zephyr-latest/boards/others/esp32c3_supermini/doc/ |
| D | index.rst | 6 ESP32-C3-SUPERMINI is based on the ESP32-C3, a single-core Wi-Fi and Bluetooth 5 (LE) microcontroll…
17 - 32-bit RISC-V single-core processor, up to 160MHz
35 - 1 x soc core temperature sensor
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| /Zephyr-latest/boards/sparkfun/thing_plus_matter_mgm240p/doc/ |
| D | index.rst | 24 - CPU core: 32-bit ARM® Cortex®-M33 core at 39 MHz
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| /Zephyr-latest/boards/nxp/imx8mn_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
8 Zephyr OS is ported to run on the Cortex®-A53 core.
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| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf91.dtsi | 52 reg-names = "wrapper", "core";
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.nrf_grtc | 56 This feature prevents the SYSCOUNTER from sleeping when any core is in
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| /Zephyr-latest/cmake/modules/ |
| D | arch.cmake | 31 # (read: multi-core and multi-arch SoC).
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| /Zephyr-latest/boards/weact/stm32f405_core/ |
| D | weact_stm32f405_core.dts | 14 compatible = "weact,stm32f405-core", "st,stm32f405";
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| /Zephyr-latest/arch/arc/ |
| D | CMakeLists.txt | 27 add_subdirectory(core)
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| /Zephyr-latest/boards/native/nrf_bsim/ |
| D | CMakeLists.txt | 10 message(FATAL_ERROR "Targeting the nrf54l15bsim/nrf54l15/cpuflpr core is not yet supported")
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| /Zephyr-latest/tests/benchmarks/posix/threads/ |
| D | README.rst | 21 API, Thread ID, time(s), threads, cores, rate (threads/s/core)
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| /Zephyr-latest/samples/bluetooth/ |
| D | bluetooth.rst | 22 and program the corresponding sample for the nRF5340 network core
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| /Zephyr-latest/samples/boards/st/power_mgmt/standby_shutdown/ |
| D | README.rst | 25 in core sleep states, as LPTIM (:dtcompatible:`st,stm32-lptim`).
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