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/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/
DREADME.rst41 [00:00:01.417,175] <inf> host: Wait 500ms. Let net core finish its sends
42 [00:00:01.917,266] <inf> host: Stop network core
44 [00:00:01.917,327] <inf> host: Run network core
/Zephyr-latest/boards/waveshare/esp32s3_touch_lcd_1_28/doc/
Dindex.rst14 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
20 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
50 ESP32-S3 allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core
51 architecture, each core can be enabled to execute customized tasks in stand-alone mode
/Zephyr-latest/boards/beagle/beaglebone_ai64/doc/
Dindex.rst35 module supports 512 interrupt inputs per R5F core. Each interrupt can be either
36 a level or a pulse (both active-high). The VIM has two interrupt outputs per core
59 the A72 core has to load the program for the R5 cores to the right memory
61 This can be done from Linux on the A72 core via remoteproc.
104 | Ensure the core is not running.
/Zephyr-latest/samples/subsys/ipc/ipc_service/static_vrings/
DKconfig8 bool "Include remote core header directory"
/Zephyr-latest/samples/subsys/ipc/openamp/
DKconfig8 bool "Include remote core header directory"
/Zephyr-latest/samples/drivers/ipm/ipm_mcux/
DKconfig8 bool "Include remote core header directory"
/Zephyr-latest/samples/drivers/mbox_data/
DKconfig8 bool "Include remote core header directory"
/Zephyr-latest/tests/drivers/mbox/mbox_data/
DKconfig8 bool "Include remote core header directory"
/Zephyr-latest/boards/phytec/phyboard_electra/doc/
Dindex.rst11 for the ARM Cortex-M4F MCU core and the following features:
30 well as a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on
31 the M4F core and the following listed hardware specifications are used:
94 cores of the SoM. These cores will then load the zephyr binary on the M4 core
107 To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following comm…
127 The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot.
/Zephyr-latest/boards/arduino/giga_r1/doc/
Dindex.rst7 STM32H747XI, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash
51 The dual core nature of STM32H747 SoC requires sharing HW resources between the
54 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
66 Applications for the ``arduino_giga_r1`` board should be built per core target,
115 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
/Zephyr-latest/boards/native/nrf_bsim/
DKconfig.defconfig10 # When the IPC service is used, the net core image requires the application core image, as it needs
/Zephyr-latest/arch/arc/core/mpu/
DKconfig18 ARC core MPU functionalities
25 If your core supports that, it is preferred over MPU stack guard.
/Zephyr-latest/boards/nxp/s32z2xxdc2/doc/
Dindex.rst194 this board from the core internal SRAM.
286 This Zephyr port can only run single core in any of the Cortex-R52 cores,
288 core of the RTU chosen and in lock-step mode (which is the reset
295 the build configuration. To debug for a core different than the default use:
303 west debug --core-name='R52_<rtu_id>_<core_id>_LS'
309 west debug --core-name='R52_<rtu_id>_<core_id>'
314 - ``<core_id>`` is the zero-based core index relative to the RTU on which to
318 ``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration:
327 To execute this sample in the second core of RTU0 in split-lock mode:
331 west debug --core-name='R52_0_1'
[all …]
/Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/
Dboard.cmake3 # During gdb session, by default connect to CM4 core.
/Zephyr-latest/tests/bluetooth/tester/
DKconfig.sysbuild12 bool "HCI IPC image on network core"
/Zephyr-latest/modules/lvgl/
DCMakeLists.txt23 ${LVGL_DIR}/src/core/lv_group.c
24 ${LVGL_DIR}/src/core/lv_obj.c
25 ${LVGL_DIR}/src/core/lv_obj_class.c
26 ${LVGL_DIR}/src/core/lv_obj_draw.c
27 ${LVGL_DIR}/src/core/lv_obj_event.c
28 ${LVGL_DIR}/src/core/lv_obj_id_builtin.c
29 ${LVGL_DIR}/src/core/lv_obj_pos.c
30 ${LVGL_DIR}/src/core/lv_obj_property.c
31 ${LVGL_DIR}/src/core/lv_obj_scroll.c
32 ${LVGL_DIR}/src/core/lv_obj_style.c
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
DKconfig.soc1 # Microchip MEC1501 MCU core series
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/bap_unicast_client/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/ccp/call_control_server/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/cap/acceptor/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/cap/initiator/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/tests/arch/arm/arm_irq_vector_table/
Dirq-vector-table.ld8 * arch/arm/core/vector_table.ld when the IRQ vector table is enabled.
/Zephyr-latest/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/
DKconfig.sysbuild9 # otherwise by default they would have gone to the net core.
/Zephyr-latest/soc/microchip/mec/mec174x/
DKconfig1 # Microchip MEC174X MCU core series

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