Searched refs:cache (Results 76 – 100 of 319) sorted by relevance
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18 cache-size = <64>;
14 cache-size = <4096>;
19 cache-size = <64>;
14 cache-size = <256>;
24 cache-size = <256>;
13 d-cache-line-size = <64>;
89 if (_kernel.ready_q.cache != _current) { in idle()
17 # ARMv8 NS world with cache management
23 # Enable cache
30 cache-size = <4096>;
100 return !memcmp(beacon->cache, params->auth, sizeof(beacon->cache)); in beacon_cache_match()105 memcpy(beacon->cache, auth, sizeof(beacon->cache)); in cache_add()110 (void)memset(sub->secure_beacon.cache, 0, sizeof(sub->secure_beacon.cache)); in bt_mesh_beacon_cache_clear()112 (void)memset(sub->priv_beacon.cache, 0, sizeof(sub->priv_beacon.cache)); in bt_mesh_beacon_cache_clear()
25 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
9 board_runner_args(openocd --gdb-init "maintenance flush register-cache")
414 transfers when cache coherence issues are not optimal or can not415 be solved using cache maintenance operations.825 This hidden configuration should be selected when the CPU has a d-cache.831 incoherent cache. This applies to intra-CPU multiprocessing837 This hidden configuration should be selected when the CPU has an i-cache.1016 bool "Data cache (d-cache) support"1020 This option enables the support for the data cache (d-cache).1023 bool "Instruction cache (i-cache) support"1027 This option enables the support for the instruction cache (i-cache).1044 This option enables the cache management functions backed by arch or[all …]
