Searched refs:aligned (Results 51 – 75 of 103) sorted by relevance
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| /Zephyr-latest/arch/arm64/core/ |
| D | mmu.c | 175 bool aligned = (desc & PTE_PHYSADDR_MASK & (level_size - 1)) == 0; in is_desc_block_aligned() local
177 if (!aligned) { in is_desc_block_aligned()
182 return aligned; in is_desc_block_aligned()
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| /Zephyr-latest/doc/kernel/services/data_passing/ |
| D | lifos.rst | 27 LIFO data items must be aligned on a word boundary, as the kernel reserves
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| D | fifos.rst | 27 FIFO data items must be aligned on a word boundary, as the kernel reserves
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| D | pipes.rst | 69 buffer capable of holding 100 bytes and is aligned to a 4-byte boundary.
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| /Zephyr-latest/samples/subsys/shell/fs/ |
| D | README.rst | 115 address. Data must be aligned to a value dependent on the target flash memory,
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | linker.ld | 209 * For performance, BSS section is assumed to be 4 byte aligned and
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| /Zephyr-latest/include/zephyr/arch/nios2/ |
| D | linker.ld | 256 * For performance, BSS section is assumed to be 4 byte aligned and
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| /Zephyr-latest/include/zephyr/arch/arc/v2/ |
| D | linker.ld | 194 * For performance, BSS section is assumed to be 4 byte aligned and
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| /Zephyr-latest/ |
| D | CODE_OF_CONDUCT.md | 48 not aligned to this Code of Conduct, and will communicate reasons for moderation
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| /Zephyr-latest/doc/kernel/usermode/ |
| D | memory_domain.rst | 191 that partitions be sized to some power of two, and aligned to their own
192 size. For MMU-based systems, the partition must be aligned to a page and
274 be properly aligned, and the total size of the region conforms to the memory
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| /Zephyr-latest/cmake/linker_script/common/ |
| D | common-rom.cmake | 35 # hence symbol __CTOR_LIST__ must be aligned on word
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| /Zephyr-latest/doc/build/cmake/ |
| D | index.rst | 187 application partitions are properly grouped and aligned for the
236 generates an app shared memory aligned linker script snippet where the
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| /Zephyr-latest/doc/services/ipc/ipc_service/backends/ |
| D | ipc_service_icmsg.rst | 112 If data caching is enabled, the shared memory region provided to ICMsg must be aligned according to…
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| /Zephyr-latest/doc/services/mem_mgmt/ |
| D | index.rst | 156 // Allocate 0x200 bytes of non-cacheable memory aligned to 32 bytes
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| /Zephyr-latest/soc/amd/acp_6_0/adsp/ |
| D | linker.ld | 399 . = ALIGN(4); /* this table MUST be 4-byte aligned */
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | linker.ld | 241 * For performance, BSS section is assumed to be 4 byte aligned and
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| /Zephyr-latest/doc/hardware/cache/ |
| D | guide.rst | 178 buffers should be aligned to the cache line size. This can be accomplished by
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| /Zephyr-latest/kernel/ |
| D | Kconfig.vm | 37 base addresses being aligned to some common value (which allows
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 153 * page-aligned or it will throw an error, not sure why since all
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| /Zephyr-latest/soc/cdns/xtensa_sample_controller/include/ |
| D | xtensa-sample-controller.ld | 488 . = ALIGN(4); /* this table MUST be 4-byte aligned */
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | linker.ld | 492 * For performance, BSS section is forced to be both 4 byte aligned and
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| /Zephyr-latest/doc/kernel/memory_management/ |
| D | heap.rst | 158 guaranteed to be aligned on a multiple of pointer sizes. If a suitable
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| /Zephyr-latest/doc/services/rtio/ |
| D | index.rst | 146 is 4 byte aligned.
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| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig | 106 are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
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| /Zephyr-latest/arch/ |
| D | Kconfig | 365 whose MPUs require regions to be power-of-two aligned/sized.
513 to be aligned to architecture specific size. The default
553 to be aligned to architecture specific size. The default
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