| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
|
| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
8 The Arduino Uno layout provides four headers, two each along
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
20 towards the top, skipping two pins, then finishing with D14 and
29 AREF -
30 GND -
[all …]
|
| D | sparkfun,micromod-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 The micromod standard consists of two lanes with the following
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
[all …]
|
| D | arduino-mkr-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Arduino MKR layout provides two headers on both edges of the board.
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
[all …]
|
| D | ene,kb1200-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 interrupt, but are assigned to two different IRQ interrupts in groups of 16
13 pins. This means that single port group provide two interrupt source.
17 compatible: "ene,kb1200-gpio"
19 include: [gpio-controller.yaml, base.yaml]
28 "#gpio-cells":
31 gpio-cells:
32 - pin
33 - flags
|
| D | arduino-nano-header-r3.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Arduino Nano layout provides two headers on opposite edges of the board.
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
10 and GND (pin 4) pins are not exposed by this binding.
11 * A 15-pin Analog Input and power supply header. This has analog input
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
31 10 D10 AREF -
[all …]
|
| D | adafruit-feather-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Feather layout provides two headers, one each along
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
[all …]
|
| D | seeed-xiao-header.yaml | 4 # SPDX-License-Identifier: Apache-2.0
9 The Seeeeduino Xiao layout provides two headers, along opposite
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
31 compatible: "seeed,xiao-gpio"
33 include: [gpio-nexus.yaml, base.yaml]
|
| /Zephyr-latest/dts/bindings/net/wireless/ |
| D | generic-fem-two-ctrl-pins.yaml | 1 # Copyright (c) 2020-2021 Nordic Semiconductor ASA
2 # SPDX-License-Identifier: Apache-2.0
5 This is a representation of generic radio Front-End Module (FEM)
6 that has a two-pin control interface (CTX, CRX).
8 The CTX control pin is used to enable the Power Amplifier (PA) in
10 the "PA pin" in other contexts.
12 The CRX control pin is used to enable the Low Noise Amplifier
14 the "LNA pin" in other contexts.
17 (Though if you do specify a pin, you must also specify its
18 corresponding settle-time-us property.)
[all …]
|
| D | nordic,nrf-radio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
15 Front-End Module (FEM) support
16 ------------------------------
18 External front-end modules are range extenders used for boosting
27 nrf_radio_fem: my-fem {
34 - generic-fem-two-ctrl-pins
35 - nordic,nrf21540-fem
41 ---------------------------
44 The 'dfe-supported' property will be set when it is available.
45 In this case, the 'dfegpio[n]-gpios' properties configure GPIO pins
[all …]
|
| /Zephyr-latest/drivers/pwm/ |
| D | Kconfig.nrf_sw | 4 # SPDX-License-Identifier: Apache-2.0
16 GPIOTE channel and two PPI/DPPI channels and per pin.
19 channel and two or three (when the fork feature is not available)
20 PPI/DPPI channels per pin.
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,iis328dq-common.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 include: sensor-device.yaml
8 int1-gpios:
9 type: phandle-array
11 INT_1 pin
13 This pin defaults to active high when produced by the sensor. The property value should ensure
16 int2-gpios:
17 type: phandle-array
19 INT_2 pin
21 This pin defaults to active high when produced by the sensor. The property value should ensure
[all …]
|
| /Zephyr-latest/samples/bluetooth/encrypted_advertising/ |
| D | README.rst | 1 .. zephyr:code-sample:: bluetooth_encrypted_advertising
3 :relevant-api: bluetooth
12 - the exchange of the session key and the initialization vector using the Key
14 - the encryption of advertising payloads,
15 - the decryption of those advertising payloads,
16 - and the update of the Randomizer field whenever the RPA is changed.
28 * Two boards with Bluetooth Low Energy support
29 * Two boards with a push button connected via a GPIO pin, see the :zephyr:code-sample:`button`
38 See :zephyr:code-sample-category:`bluetooth` samples for details.
40 This sample uses two applications, so two devices need to be setup.
[all …]
|
| /Zephyr-latest/dts/bindings/regulator/ |
| D | nordic,npm1300-regulator.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The PMIC has two buck converters and two LDOs.
16 compatible = "nordic,npm1300-regulator";
33 compatible: "nordic,npm1300-regulator"
38 dvs-gpios:
39 type: phandle-array
43 DVS mode 1 will enable the first pin
44 DVS mode 2 will enable the second pin
47 The effect of the mode change is defined by the enable-gpios
50 child-binding:
[all …]
|
| /Zephyr-latest/samples/boards/nordic/dynamic_pinctrl/ |
| D | README.rst | 1 .. zephyr:code-sample:: nrf_dynamic_pinctrl
2 :name: Dynamic Pin Control
4 Dynamically change pin configuration at boot time.
6 The Dynamic Pin Control (nRF) sample demonstrates how to change ``uart0`` at
7 early boot stages, depending on the input level on a pin connected to a
8 push-button.
22 The Dynamic Pin Control (nRF) sample allows you to select the appropriate routing.
38 .. figure:: images/nrf52840dk-dynamic-pinctrl.webp
54 .. zephyr-app-commands::
55 :zephyr-app: samples/boards/nordic/dynamic_pinctrl
[all …]
|
| /Zephyr-latest/boards/silabs/radio_boards/ |
| D | index.rst | 20 There are two main variants of the Mainboard:
22 - Wireless Starter Kit Mainboard (board BRD4001A, available standalone as SLWMB4001A)
23 - Wireless Pro Kit Mainboard (board BRD4002A, available standalone as Si-MB4002A)
26 the two boards are pin compatible for all shared functionality.
40 - Advanced Energy Monitor providing real-time information about energy consumption at up to 10 ksps
41 - Packet Trace Interface
42 - Virtual COM port
43 - On-board Segger J-Link debugger with USB and Ethernet interfaces
44 - Ultra-low power 128x128 pixel memory LCD
45 - 2 user buttons and 2 LEDs
[all …]
|
| /Zephyr-latest/dts/bindings/mfd/ |
| D | nordic,npm1300.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: i2c-device.yaml
14 host-int-gpios:
15 type: phandle-array
16 description: Host pin for interrupt input
18 pmic-int-pin:
20 description: Pmic pin number for interrupt output
22 ship-to-active-time-ms:
28 - 16
29 - 32
[all …]
|
| /Zephyr-latest/boards/shields/arduino_uno_click/boards/ |
| D | nrf9160dk_nrf9160_arduino_uno_click_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 * The original Arduino Uno provides the same SCL/SDA on two sets of
10 * pins, but the nRF9160 DK maps these pins to two different pairs of
25 low-power-enable;
30 * The default pin group for the nRF9160 DK includes RTS/CTS HW flow
33 * on the same pins, but just removes RTS/CTS from the pin groups.
46 low-power-enable;
|
| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/ |
| D | README.txt | 1 GPIO 2-Pin Test
5 where two GPIOs are directly wired together. The test pins are
6 identified through a test-specific devicetree binding in the `dts/`
19 FATAL output pin not wired to input pin? (out high => in low)
|
| /Zephyr-latest/tests/drivers/pwm/pwm_loopback/dts/bindings/ |
| D | test-pwm-loopback.yaml | 2 # Copyright (c) 2020-2021 Vestas Wind Systems A/S
4 # SPDX-License-Identifier: Apache-2.0
11 compatible: "test-pwm-loopback"
15 type: phandle-array
18 PWM pins that will be used for generating and capturing a pulse-width
19 modulated signal. The pin at the first index will be used for signal
20 generation while the pin at the second index will be used for capuring
21 the generated signal. The two pins must be physically connected to
|
| /Zephyr-latest/include/zephyr/dt-bindings/gpio/ |
| D | espressif-esp32-gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
16 * The interface supports two different drive strengths:
17 * `DFLT` - The lowest drive strength supported by the HW
18 * `ALT` - The highest drive strength supported by the HW
36 * @name GPIO pin input/output enable flags
38 * These flags allow configuring a pin as input or output while keeping untouched
39 * its complementary configuration. By instance, if we configure a GPIO pin as an
41 * pin's output buffer. This functionality can be useful to render a pin both an
47 /** Keep GPIO pin enabled as output */
50 /** Keep GPIO pin enabled as input */
|
| /Zephyr-latest/samples/boards/bbc/microbit/pong/ |
| D | README.rst | 1 .. zephyr:code-sample:: bbc_microbit_pong
4 Play pong as single player or over Bluetooth between two micro:bit devices.
9 Play pong as single player or over Bluetooth between two micro:bit
12 The game works by controlling a paddle with the two buttons of the
14 button A to toggle between single- and multi-player, and press button B
18 When multi-player mode has been selected the game will try to look for
19 and connect to a second micro:bit which has also been set into multi-player
22 If the board has a piezo buzzer connected to pin 0, this will be used to
28 .. zephyr-app-commands::
29 :zephyr-app: samples/boards/bbc/microbit/pong
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,flexio-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 The two PWM modes supported by flexio are chosen based on the selected polarity -
7 Dual 8-bit counters PWM mode and Dual 8-bit counters PWM Low mode.
9 compatible: "nxp,flexio-pwm"
11 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 "#pwm-cells":
23 pwm-cells:
24 - channel
[all …]
|
| D | infineon,xmc4xxx-ccu8-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
15 transitions from 0 to 1, preventing the high-side and low-side
18 There are two CCU8 modules with DTS node labels: pwm_ccu80 and
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
25 defined by the 'slice-prescaler' property. Additionally, each
[all …]
|
| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_port.c | 5 * SPDX-License-Identifier: Apache-2.0
9 * @brief Atmel SAM0 MCU family I/O Pin Controller (PORT)
16 int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func) in soc_port_pinmux_set() argument
18 bool is_odd = pin & 1; in soc_port_pinmux_set()
19 int idx = pin / 2U; in soc_port_pinmux_set()
21 /* Each pinmux register holds the config for two pins. The in soc_port_pinmux_set()
22 * even numbered pin goes in the bits 0..3 and the odd in soc_port_pinmux_set()
23 * numbered pin in bits 4..7. in soc_port_pinmux_set()
26 pg->PMUX[idx].bit.PMUXO = func; in soc_port_pinmux_set()
28 pg->PMUX[idx].bit.PMUXE = func; in soc_port_pinmux_set()
[all …]
|
