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/Zephyr-latest/modules/hal_nordic/nrfs/dvfs/
Dld_dvfs.c45 LOG_DBG("REGW: NRF_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
47 (uint32_t)&NRF_ABB->TRIM.RINGO[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
49 LOG_DBG("REGW: NRF_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
51 (uint32_t)&NRF_ABB->TRIM.LOCKRANGE[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
53 LOG_DBG("REGW: NRF_ABB->TRIM.PVTMONCYCLES[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
55 (uint32_t)&NRF_ABB->TRIM.PVTMONCYCLES[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
59 LOG_DBG("REGW: NRF_APPLICATION_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
61 (uint32_t)&NRF_APPLICATION_ABB->TRIM.RINGO[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
63 LOG_DBG("REGW: NRF_APPLICATION_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
65 (uint32_t)&NRF_APPLICATION_ABB->TRIM.LOCKRANGE[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
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Dld_dvfs_handler.c281 LOG_DBG("Trim ABB for default voltage."); in dvfs_service_handler_task()
/Zephyr-latest/soc/nordic/nrf92/
Dsoc.c61 nrf_hsfll_trim_t trim = { in trim_hsfll() local
67 LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup); in trim_hsfll()
68 LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse); in trim_hsfll()
69 LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine); in trim_hsfll()
74 nrf_hsfll_trim_set(hsfll, &trim); in trim_hsfll()
78 LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); in trim_hsfll()
79 LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); in trim_hsfll()
80 LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE); in trim_hsfll()
/Zephyr-latest/soc/nordic/nrf54h/
Dsoc.c90 nrf_hsfll_trim_t trim = { in trim_hsfll() local
96 LOG_DBG("Trim: HSFLL VSUP: 0x%.8x", trim.vsup); in trim_hsfll()
97 LOG_DBG("Trim: HSFLL COARSE: 0x%.8x", trim.coarse); in trim_hsfll()
98 LOG_DBG("Trim: HSFLL FINE: 0x%.8x", trim.fine); in trim_hsfll()
103 nrf_hsfll_trim_set(hsfll, &trim); in trim_hsfll()
109 LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); in trim_hsfll()
110 LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); in trim_hsfll()
111 LOG_DBG("NRF_HSFLL->TRIM.FINE = %d", hsfll->TRIM.FINE); in trim_hsfll()
/Zephyr-latest/dts/bindings/usb/
Dnxp,usbphy.yaml18 It is board level's value that is used to trim the nominal 17.78mA
25 It is board level's value that is used to trim the nominal 17.78mA
32 It is board level's value that is used to trim the nominal 17.78mA
/Zephyr-latest/soc/ti/simplelink/cc13x2_cc26x2/
Dsoc.c14 /* Performs necessary trim of the device. */ in soc_early_init_hook()
/Zephyr-latest/soc/ti/simplelink/cc13x2x7_cc26x2x7/
Dsoc.c14 /* Performs necessary trim of the device. */ in soc_early_init_hook()
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dboard.c220 /* Trim FRO to 192MHz */ in power_manager_set_profile()
242 /* Trim the FRO to 96MHz */ in power_manager_set_profile()
322 /* Read 192M FRO clock Trim settings from fuses. in mimxrt595_evk_init()
328 /* Read 96M FRO clock Trim settings from fuses. */ in mimxrt595_evk_init()
333 * Production devices have 96M trim values programmed in OTP fuses. in mimxrt595_evk_init()
337 /* If not programmed then use software to calculate the trim values */ in mimxrt595_evk_init()
/Zephyr-latest/doc/develop/toolchains/
Dzephyr_sdk.rst105 tar xvf zephyr-sdk- |sdk-version-trim| _linux-x86_64.tar.xz
139 …sudo cp ~/zephyr-sdk- |sdk-version-trim| /sysroots/x86_64-pokysdk-linux/usr/share/openocd/contrib/…
161 tar xvf zephyr-sdk- |sdk-version-trim| _macos-x86_64.tar.xz
207 7z x zephyr-sdk- |sdk-version-trim| _windows-x86_64.7z
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-hsfll-local.yaml23 Required FICR entries are for VSUP, COARSE and FINE trim values.
/Zephyr-latest/modules/segger/
DKconfig56 bool "Trim: Do not block, output as much as fits."
/Zephyr-latest/drivers/hwinfo/
Dhwinfo_ambiq.c20 /* Ambiq Factory Trim Revision */ in z_impl_hwinfo_get_device_id()
/Zephyr-latest/subsys/logging/
DKconfig.misc91 mode is tracked. It can be used to trim LOG_BUFFER_SIZE.
/Zephyr-latest/doc/develop/sca/
Dcodechecker.rst72 - Trim the defined path from the analysis results, e.g. ``/home/user/zephyrproject``.
/Zephyr-latest/cmake/sca/codechecker/
Dsca.cmake60 set(CODECHECKER_TRIM_PATH_PREFIX "--trim-path-prefix;${CODECHECKER_TRIM_PATH_PREFIX}")
/Zephyr-latest/modules/hal_gigadevice/
DKconfig116 Enable GD32 Clock Trim Controller (CTC) HAL module driver
/Zephyr-latest/samples/net/sockets/echo_server/src/ws_console/
Dindex.html24 zconsole(new Date().timeNow() + " : " + e.data.trim());
/Zephyr-latest/samples/net/sockets/big_http_download/src/
Dbig_http_download.c169 /* Trim LF. */ in parse_header()
178 /* Trim CR if present. */ in parse_header()
/Zephyr-latest/doc/
Dconf.py147 .. |sdk-version-trim| unicode:: {sdk_version}
148 :trim:
/Zephyr-latest/scripts/
Dcheckpatch.pl681 return trim($string) if ($string =~ /^\s*0[0-7]{3,3}\s*$/);
1167 $name = trim($name);
1182 $name = trim($name);
1184 $address = trim($address);
1200 $name = trim($name);
1202 $address = trim($address);
2237 sub trim { subroutine
3918 …"Prefer '" . trim($sign) . " int" . rtrim($pointer) . "' to bare use of '$sign" . rtrim($pointer) …
3920 my $decl = trim($sign) . " int ";
3994 my $comment = trim($1);
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/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c65 LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM); in vbat_clock_regs()
/Zephyr-latest/drivers/sensor/bosch/bmm150/
Dbmm150.c598 /* Reads the trim registers of the sensor */ in bmm150_init_chip()
601 LOG_ERR("failed to read trim regs"); in bmm150_init_chip()
/Zephyr-latest/doc/develop/getting_started/
Dinstallation_linux.rst247 tar xvf zephyr-sdk- |sdk-version-trim| _linux-x86_64.tar.xz
/Zephyr-latest/subsys/mgmt/mcumgr/smp/src/
Dsmp.c457 /* Trim processed request to free up space for subsequent responses. */ in smp_process_request_packet()
/Zephyr-latest/drivers/sensor/bosch/bmc150_magn/
Dbmc150_magn.c538 LOG_ERR("failed to read trim regs"); in bmc150_magn_init_chip()

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