| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,xps-gpio-1.00.a.yaml | 3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
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| /Zephyr-Core-3.5.0/boards/arm/arty/dts/ |
| D | arty_a7_arm_designstart.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
95 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
105 compatible = "gpio-keys";
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_xlnx_axi.c | 4 * SPDX-License-Identifier: Apache-2.0
54 uint32_t tri; member
60 /* Workaround to handle channel 2 interrupts from channel 1*/
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
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| D | gpio_ite_it8xxx2_v2.c | 4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
18 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
69 const struct gpio_ite_cfg *gpio_config = dev->config; in gpio_ite_configure()
70 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr; in gpio_ite_configure()
71 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr; in gpio_ite_configure()
72 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr; in gpio_ite_configure()
73 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin; in gpio_ite_configure()
74 struct gpio_ite_data *data = dev->data; in gpio_ite_configure()
80 return -ENOTSUP; in gpio_ite_configure()
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| D | gpio_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) : in wuesr()
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5)); in wuesr()
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_xlnx_axi_quadspi.c | 4 * SPDX-License-Identifier: Apache-2.0
18 /* AXI Quad SPI v3.2 register offsets (See Xilinx PG153 for details) */
37 #define SPICR_MASTER BIT(2)
49 #define SPISR_TX_EMPTY BIT(2)
71 #define IPIXR_DTR_EMPTY BIT(2)
98 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
100 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
107 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
109 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
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| D | spi_xec_qmspi_ldma.c | 4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
84 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
99 uint8_t np; /* number of data pins: 1, 2, or 4 */
105 uint32_t tempbuf[2];
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
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| D | spi_xec_qmspi.c | 4 * SPDX-License-Identifier: Apache-2.0
29 uint8_t width; /* 1(single), 2(dual), 4(quad) */
42 ((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2); in descr_rd()
50 ((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2); in descr_wr()
57 REG8(®s->TX_FIFO) = data8; in txb_wr8()
62 return REG8(®s->RX_FIFO); in rxb_rd8()
86 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
88 regs->MODE = qmode; in qmspi_set_frequency()
102 * 2 1 0
128 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
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| /Zephyr-Core-3.5.0/subsys/mgmt/osdp/ |
| D | Kconfig.pd | 4 # SPDX-License-Identifier: Apache-2.0
11 default 1
18 default 16
26 default 1
38 default "NONE"
43 channel with default SCBK. Once as secure channel is active with the
44 default key, the CP can send a KEYSET command to set new keys to the PD.
54 default 0x001A2B3C
61 default 1
68 default 1
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | xlnx,pinctrl-zynq.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21 pinctrl_uart1_default: uart1-default {
29 slew-rate = <IO_SPEED_SLOW>;
30 power-source = <IO_STANDARD_LVCMOS18>;
33 conf-rx {
35 bias-high-impedance;
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/ |
| D | soc_espi_saf_v1.h | 4 * SPDX-License-Identifier: Apache-2.0
18 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
31 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
34 /* Default SAF Map of eSPI TAG numbers to master numbers */
40 * Default QMSPI clock divider and chip select timing.
43 #define MCHP_SAF_QMSPI_CLK_DIV 2U
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
102 MCHP_QMSPI_C_XFR_NUNITS(2) | \
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/ |
| D | soc_espi_saf_v2.h | 4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
30 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2u
33 /* Default SAF Map of eSPI TAG numbers to master numbers */
39 * Default QMSPI clock divider and chip select timing.
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
126 MCHP_QMSPI_C_XFR_NUNITS(2) | \
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| /Zephyr-Core-3.5.0/boards/arm/lpcxpresso11u68/doc/ |
| D | index.rst | 10 on an ARM Cortex-M0+ core.
21 - LPC11U68 microcontroller in LQFP100 package
22 - ARM Cortex-M0+
23 - Memory:
25 - 256KB of flash memory
26 - 32KB of SRAM
27 - 2x2KB of additional SRAM
28 - 4 KB EEPROM
29 - USB:
31 - USB 2.0 Full-Speed device controller
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| /Zephyr-Core-3.5.0/scripts/kconfig/ |
| D | guiconfig.py | 4 # SPDX-License-Identifier: ISC
10 # pylint: disable=undefined-variable
16 A Tkinter-based menuconfig implementation, based around a treeview control and
18 ('make xconfig'). Compatible with both Python 2 and Python 3.
21 single menu (like menuconfig.py). Only single-menu mode distinguishes between
24 A show-all mode is available that shows invisible items in red.
29 Ctrl-S : Save configuration
30 Ctrl-O : Open configuration
31 Ctrl-A : Toggle show-all mode
32 Ctrl-N : Toggle show-name mode
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| /Zephyr-Core-3.5.0/boards/arm/frdm_kl25z/doc/ |
| D | index.rst | 3 NXP FRDM-KL25Z
9 The Freedom KL25Z is an ultra-low-cost development platform for
11 on ARM |reg| Cortex |reg|-M0+ processor.
13 The FRDM-KL25Z features include easy access to MCU I/O, battery-ready,
14 low-power operation, a standard-based form factor with expansion board
15 options and a built-in debug interface for flash programming and run-control.
20 :alt: FRDM-KL25Z
25 - MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP
26 - On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED
27 - OpenSDA debug interface
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| /Zephyr-Core-3.5.0/boards/arm/frdm_k82f/doc/ |
| D | index.rst | 3 NXP FRDM-K82F
9 The FRDM-K82F is a low-cost development platform for Kinetis K80, K81,
12 - Form-factor compatible with the Arduino R3 pin layout
13 - Peripherals enable rapid prototyping, including a six-axis digital
15 tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb
17 with Bluetooth and 2.4 GHz radio add-on modules
18 - OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter
20 flash programming, and run-control debugging
24 :alt: FRDM-K82F
29 - MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power,
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| /Zephyr-Core-3.5.0/boards/arm/frdm_k22f/doc/ |
| D | index.rst | 3 NXP FRDM-K22F
9 The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22
12 - Form-factor compatible with the Arduino R3 pin layout
13 - Peripherals enable rapid prototyping, including a 6-axis digital
15 tri-colored LED and 2 user push-buttons for direct interaction, a optional
17 add-on modules
18 - OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
20 flash programming, and run-control debugging
24 :alt: FRDM-K22F
29 - MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power,
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_mchp_xec_v2.c | 5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
29 #define SPEED_1MHZ_BUS 2
69 #define I2C_XEC_STATE_OPEN 2U
73 #define I2C_XEC_ERR_BUS 2
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
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| /Zephyr-Core-3.5.0/boards/arm/frdm_k64f/doc/ |
| D | index.rst | 3 NXP FRDM-K64F
9 The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64,
12 - Form-factor compatible with the Arduino R3 pin layout
13 - Peripherals enable rapid prototyping, including a 6-axis digital
15 tri-colored LED and 2 user push-buttons for direct interaction, a microSD
17 with Bluetooth* and 2.4 GHz radio add-on modules
18 - OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
20 flash programming, and run-control debugging
24 :alt: FRDM-K64F
29 - MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power,
[all …]
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