| /hal_gigadevice-latest/pinconfigs/ |
| D | gd32vf103xx.yml | 9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
383 pins:
627 pins: [PA11, null, PB8, PD0]
629 pins: [PA12, null, PB9, PD1]
631 pins: [PB12, PB5]
633 pins: [PB13, PB6]
635 pins: [PB6, PB8]
[all …]
|
| D | gd32e507xx.yml | 9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
701 pins:
1041 pins: [PA11, null, PB8, PD0]
1043 pins: [PA12, null, PB9, PD1]
1045 pins: [PB12, PB5]
1047 pins: [PB13, PB6]
1049 pins: [PA8, PD15, null, PF0]
1051 pins: [PA7, PD8]
[all …]
|
| D | gd32f403xx.yml | 9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
484 pins:
824 pins: [PA11, null, PB8, PD0]
826 pins: [PA12, null, PB9, PD1]
828 pins: [PB12, PB5]
830 pins: [PB13, PB6]
832 pins: [PA8, PD15, null, PF0]
834 pins: [PB6, PB8]
[all …]
|
| D | gd32e103xx.yml | 9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
450 pins:
694 pins: [PB6, PB8]
696 pins: [PB7, PB9]
698 pins: [PB5, PC12]
700 pins: [PA15, PA4]
702 pins: [PB3, PC10]
[all …]
|
| D | README.md | 12 different set of pins. For this reason we will name the model used by such
31 combinations, either because of a different number of pins or because devices
70 - `pins` (required): A dictionary of pin configurations.
82 - `pins`: Available pins. The size of the list of pins determines wether
101 pins:
112 pins: [PA11, PB8, None, PD0]
131 - `pins` (required): Configuration for all pins.
147 pins:
164 For GD32F405Vx series, LQFP100 package have 82 I/O pins, but BGA100 package only have 81 I/O pins. …
168 This issue cause by peripheral number increased on GD32F350xB/8/6, related pins already mapping
[all …]
|
| D | gd32f350xx.yml | 8 # - 28 pins: G
9 # - 32 pins: K
10 # - 48 pins: C
11 # - 64 pins: R
88 pins:
|
| D | gd32a503xx.yml | 8 # - 32 pins: K
9 # - 48 pins: C
10 # - 64 pins: R
11 # - 100 pins: V
36 pins:
|
| D | gd32l233xx.yml | 9 # - 32 pins: Q (GD32L233Kx-QFN32)
10 # - 32 pins: K (GD32L233Kx-LQFP32)
11 # - 48 pins: C
12 # - 64 pins: R
145 pins:
|
| D | gd32f405xx.yml | 8 # - 64 pins: R
9 # - 100 pins: V
10 # - 144 pins: Z
33 pins:
|
| D | gd32f407xx.yml | 8 # - 64 pins: R
9 # - 100 pins: V
10 # - 144 pins: Z
11 # - 176 pins: I
36 pins:
|
| D | gd32f450xx.yml | 8 # - 176 pins: I
9 # - 144 pins: Z
10 # - 100 pins: V
34 pins:
|
| D | gd32f470xx.yml | 8 # - 176 pins: I
9 # - 144 pins: Z
10 # - 100 pins: V
34 pins:
|
| /hal_gigadevice-latest/scripts/ |
| D | gd32pinctrl.py | 125 def build_afio_pin_cfgs(variant, signal_configs, pins, remaps): argument
131 pins: Pins description.
135 Dictionary with pins configuration.
155 for pin, pin_cfg in pins.items():
165 for pin in signal_remaps["pins"]:
169 if pincode in pins[pin]["pincodes"]:
206 for pin, pin_cfg in pins.items():
216 def build_af_pin_cfgs(variant, signal_configs, pins): argument
222 pins: Pins description.
225 Dictionary with pins configuration.
[all …]
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| /hal_gigadevice-latest/scripts/tests/gd32pinctrl/data/ |
| D | gd32f999xx.yml | 37 pins:
59 pins: [PA0, PA1]
61 pins: [PA1, PA0]
63 pins: [PA2, null, PA3, PA4]
65 pins: [PA3, null, PA4, PA5]
67 pins: [PA4, null, PA5, PA2]
69 pins: [PA5, null, PA2, PA3]
|
| D | gd32f888xx.yml | 27 pins:
|
| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_syscfg.c | 114 \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins
128 \arg SYSCFG_PA9_PA12_REMAP: PA9/PA12 pins are mapping on PA10/PA11 pins
|
| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_gpio.c | 280 \brief get GPIO all pins input status
285 \retval state of GPIO all pins
313 \brief get GPIO all pins output status
318 \retval state of GPIO all pins
|
| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_gpio.c | 140 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
164 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
274 \retval input status of gpio all pins
303 \retval output status of gpio all pins
|
| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_gpio.c | 157 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
181 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
290 \retval input status of gpio all pins
319 \retval output status of gpio all pins
|
| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_gpio.c | 148 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
172 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
281 \retval input status of gpio all pins
310 \retval output status of gpio all pins
|
| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_gpio.c | 281 \brief get GPIO all pins input status
286 \retval input status of GPIO all pins
319 \retval output status of GPIO all pins
|
| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_lpuart.h | 79 #define LPUART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
232 /* swap TX/RX pins */
233 LPUART_SWAP_ENABLE, /*!< swap TX/RX pins */
234 LPUART_SWAP_DISABLE, /*!< not swap TX/RX pins */
|
| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_gpio.c | 157 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
181 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
290 \retval input status of gpio all pins
319 \retval output status of gpio all pins
|
| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_syscfg.h | 58 … /*!< PA9 and PA12 remapping bit for small packages (32 pins) */
142 … SYSCFG_CFG0_PA9_PA12_RMP /*!< PA9/PA12 pins are mapping on PA10/PA11 pins */
|
| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_gpio.c | 267 \retval state of GPIO all pins
300 \retval state of GPIO all pins
|
