| /Zephyr-latest/samples/subsys/tracing/src/ |
| D | tracing_user.c | 4 * SPDX-License-Identifier: Apache-2.0
17 __ASSERT_NO_MSG(nested_interrupts[_current_cpu->id] == 0); in sys_trace_thread_switched_in_user()
28 __ASSERT_NO_MSG(nested_interrupts[_current_cpu->id] == 0); in sys_trace_thread_switched_out_user()
40 printk("%s: %d\n", __func__, nested_interrupts[curr_cpu->id]); in sys_trace_isr_enter_user()
41 nested_interrupts[curr_cpu->id]++; in sys_trace_isr_enter_user()
51 nested_interrupts[curr_cpu->id]--; in sys_trace_isr_exit_user()
52 printk("%s: %d\n", __func__, nested_interrupts[curr_cpu->id]); in sys_trace_isr_exit_user()
62 void sys_trace_gpio_pin_configure_enter_user(const struct device *port, gpio_pin_t pin, in sys_trace_gpio_pin_configure_enter_user() argument
65 printk("port: %s, pin: %d flags: %d\n", port->name, pin, flags); in sys_trace_gpio_pin_configure_enter_user()
68 void sys_trace_gpio_pin_configure_exit_user(const struct device *port, gpio_pin_t pin, int ret) in sys_trace_gpio_pin_configure_exit_user() argument
[all …]
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_nrfx.c | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nordic-nrf-gpio.h>
41 return port->data; in get_port_data()
46 return port->config; in get_port_cfg()
51 return cfg->gpiote.p_reg != NULL; in has_gpiote()
70 if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { in gpio_nrfx_gpd_retain_set()
74 nrf_gpio_port_retain_enable(cfg->port, mask); in gpio_nrfx_gpd_retain_set()
96 if (cfg->pad_pd == NRF_GPD_FAST_ACTIVE1) { in gpio_nrfx_gpd_retain_clear()
104 nrf_gpio_port_retain_disable(cfg->port, mask); in gpio_nrfx_gpd_retain_clear()
114 static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin, in gpio_nrfx_pin_configure() argument
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| D | gpio_smartbond.c | 4 * SPDX-License-Identifier: Apache-2.0
27 * data access, bit access, mode, latch and wake-up controller are defined in
67 * GPIOx_NGPIOS words for each pin mode
95 WAKEUP->WKUP_CTRL_REG = 0; in gpio_smartbond_wkup_init()
96 WAKEUP->WKUP_CLEAR_P0_REG = 0xffffffff; in gpio_smartbond_wkup_init()
97 WAKEUP->WKUP_CLEAR_P1_REG = 0xffffffff; in gpio_smartbond_wkup_init()
98 WAKEUP->WKUP_SELECT_P0_REG = 0; in gpio_smartbond_wkup_init()
99 WAKEUP->WKUP_SELECT_P1_REG = 0; in gpio_smartbond_wkup_init()
100 WAKEUP->WKUP_SEL_GPIO_P0_REG = 0; in gpio_smartbond_wkup_init()
101 WAKEUP->WKUP_SEL_GPIO_P1_REG = 0; in gpio_smartbond_wkup_init()
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| D | gpio_sam0.c | 5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/atmel-sam0-gpio.h>
28 uint8_t id; member
47 gpio_fire_callbacks(&data->callbacks, data->dev, pins); in gpio_sam0_isr()
51 static int gpio_sam0_config(const struct device *dev, gpio_pin_t pin, in gpio_sam0_config() argument
54 const struct gpio_sam0_config *config = dev->config; in gpio_sam0_config()
55 struct gpio_sam0_data *data = dev->data; in gpio_sam0_config()
56 PortGroup *regs = config->regs; in gpio_sam0_config()
62 return -ENOTSUP; in gpio_sam0_config()
72 return -ENOTSUP; in gpio_sam0_config()
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| D | gpio_lmp90xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
37 gpio_pin_t pin, gpio_flags_t flags) in gpio_lmp90xxx_config() argument
39 const struct gpio_lmp90xxx_config *config = dev->config; in gpio_lmp90xxx_config()
42 if (pin > LMP90XXX_GPIO_MAX) { in gpio_lmp90xxx_config()
43 return -EINVAL; in gpio_lmp90xxx_config()
47 return -ENOTSUP; in gpio_lmp90xxx_config()
51 return -ENOTSUP; in gpio_lmp90xxx_config()
56 return -ENOTSUP; in gpio_lmp90xxx_config()
61 err = lmp90xxx_gpio_set_input(config->parent, pin); in gpio_lmp90xxx_config()
65 err = lmp90xxx_gpio_set_pin_value(config->parent, pin, in gpio_lmp90xxx_config()
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| D | gpio_ads114s0x.c | 4 * SPDX-License-Identifier: Apache-2.0
36 static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_ads114s0x_config() argument
38 const struct gpio_ads114s0x_config *config = dev->config; in gpio_ads114s0x_config()
42 return ads114s0x_gpio_deconfigure(config->parent, pin); in gpio_ads114s0x_config()
46 return -ENOTSUP; in gpio_ads114s0x_config()
50 return -ENOTSUP; in gpio_ads114s0x_config()
55 return -ENOTSUP; in gpio_ads114s0x_config()
60 err = ads114s0x_gpio_set_input(config->parent, pin); in gpio_ads114s0x_config()
63 err = ads114s0x_gpio_set_output(config->parent, pin, in gpio_ads114s0x_config()
67 return -ENOTSUP; in gpio_ads114s0x_config()
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| D | gpio_gecko.c | 4 * SPDX-License-Identifier: Apache-2.0
26 #if DT_NODE_HAS_PROP(id, peripheral_id)
27 #define GET_GECKO_GPIO_INDEX(id) DT_INST_PROP(id, peripheral_id) argument
41 #define GET_GECKO_GPIO_INDEX(id) (DT_INST_REG_ADDR(id) - DT_REG_ADDR(DT_NODELABEL(gpioa))) \ argument
43 #endif /* DT_NODE_HAS_PROP(id, peripheral_id) */
48 * See https://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf
53 * @param[in] pin The index of the pin. Valid values are 0..7.
57 #define GECKO_GPIO_MODEL(pin, mode) (mode << (pin * 4)) argument
61 * @param[in] pin The index of the pin. Valid values are 8..15.
65 #define GECKO_GPIO_MODEH(pin, mode) (mode << ((pin - 8) * 4)) argument
[all …]
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| /Zephyr-latest/dts/bindings/serial/ |
| D | silabs,gecko-usart.yaml | 3 compatible: "silabs,gecko-usart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
14 peripheral-id:
16 description: peripheral ID
18 # Note: Not all SoC series support setting individual pin location. If this
19 # is a case all location-* properties need to have identical value.
21 location-rx:
23 description: RX pin configuration defined as <location port pin>
25 location-tx:
27 description: TX pin configuration defined as <location port pin>
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| D | silabs,gecko-leuart.yaml | 3 compatible: "silabs,gecko-leuart"
5 include: uart-controller.yaml
14 peripheral-id:
17 description: peripheral ID
19 # Note: Not all SoC series support setting individual pin location. If this
20 # is a case all location-* properties need to have identical value.
22 location-rx:
25 description: RX pin configuration defined as <location port pin>
27 location-tx:
30 description: TX pin configuration defined as <location port pin>
|
| D | silabs,gecko-uart.yaml | 3 compatible: "silabs,gecko-uart"
5 include: uart-controller.yaml
14 peripheral-id:
17 description: peripheral ID
19 # Note: Not all SoC series support setting individual pin location. If this
20 # is a case all location-* properties need to have identical value.
22 location-rx:
25 description: RX pin configuration defined as <location port pin>
27 location-tx:
30 description: TX pin configuration defined as <location port pin>
|
| D | cypress,psoc6-uart.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "cypress,psoc6-uart"
9 include: [uart-controller.yaml, pinctrl-device.yaml]
18 peripheral-id:
20 description: peripheral ID
23 pinctrl-0:
26 Port pin configuration for RX & TX signals. We expect that the
29 form p<port>_<pin>_<periph><inst>_<signal>.
32 pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
|
| /Zephyr-latest/dts/bindings/spi/ |
| D | silabs,gecko-spi-usart.yaml | 3 compatible: "silabs,gecko-spi-usart"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
14 peripheral-id:
16 description: peripheral ID
18 # Note: Not all SoC series support setting individual pin location. If this
19 # is a case all location-* properties need to have identical value.
21 location-rx:
23 description: RX pin configuration defined as <location port pin>
25 location-tx:
27 description: TX pin configuration defined as <location port pin>
[all …]
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| D | cypress,psoc6-spi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "cypress,psoc6-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 peripheral-id:
19 description: peripheral ID
22 pinctrl-0:
25 Port pin configuration for the various SPI signals that includes
29 and be of the form p<port>_<pin>_<periph><inst>_<signal>.
32 pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk &p12_3_spi6_sel0>;
|
| /Zephyr-latest/subsys/shell/modules/kernel_service/thread/ |
| D | pin.c | 4 * SPDX-License-Identifier: Apache-2.0
21 shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); in cmd_kernel_thread_pin()
26 shell_error(sh, "Invalid thread id %p", (void *)thread); in cmd_kernel_thread_pin()
27 return -EINVAL; in cmd_kernel_thread_pin()
32 shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); in cmd_kernel_thread_pin()
36 shell_print(sh, "Pinning %p %s to CPU %d", (void *)thread, thread->name, cpu); in cmd_kernel_thread_pin()
39 shell_error(sh, "Failed - %d", err); in cmd_kernel_thread_pin()
41 shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, in cmd_kernel_thread_pin()
42 thread->base.cpu_mask); in cmd_kernel_thread_pin()
48 KERNEL_THREAD_CMD_ARG_ADD(pin, NULL,
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1a/legacy/ |
| D | psoc6.dtsi | 3 * Copyright (c) 2020-2021, ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "psoc6-pinctrl.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
25 compatible = "arm,cortex-m4f";
30 flash-controller@40250000 {
31 compatible = "cypress,psoc6-flash-controller";
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| /Zephyr-latest/dts/x86/intel/ |
| D | elkhart_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
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| D | raptor_lake_p.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
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| D | raptor_lake_s.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
8 * Public APIs for pin control drivers
15 * @brief Pin Controller Interface
16 * @defgroup pinctrl_interface Pin Controller Interface
36 * @name Pin control states
51 /** Pin control state configuration. */
53 /** Pin configurations. */
55 /** Number of pin configurations. */
58 uint8_t id; member
61 /** Pin controller configuration for a given device. */
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_imx_scmi.c | 4 * SPDX-License-Identifier: Apache-2.0
10 static int scmi_pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in scmi_pinctrl_configure_pin() argument
18 settings.id = (pin->pinmux.mux_register - IOMUXC_MUXREG) / 4; in scmi_pinctrl_configure_pin()
20 settings.config[1] = IOMUXC_INPUT_ENABLE(pin->pin_ctrl_flags) in scmi_pinctrl_configure_pin()
21 ? (pin->pinmux.mux_mode | IOMUXC_SION(1)) in scmi_pinctrl_configure_pin()
22 : pin->pinmux.mux_mode; in scmi_pinctrl_configure_pin()
25 if (pin->pinmux.input_register) { in scmi_pinctrl_configure_pin()
27 settings.config[3] = (pin->pinmux.input_register - IOMUXC_DAISYREG) / 4; in scmi_pinctrl_configure_pin()
31 settings.config[5] = pin->pinmux.input_daisy; in scmi_pinctrl_configure_pin()
45 settings.id = (pin->pinmux.config_register - IOMUXC_CFGREG) / 4; in scmi_pinctrl_configure_pin()
[all …]
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| /Zephyr-latest/dts/bindings/mtd/ |
| D | atmel,at45.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [spi-device.yaml]
11 jedec-id:
12 type: uint8-array
14 description: JEDEC ID as manufacturer ID (1 byte) and device ID (2 bytes).
21 sector-size:
26 sector-0a-pages:
38 block-size:
43 page-size:
48 no-chip-erase:
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,flexio-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 The two PWM modes supported by flexio are chosen based on the selected polarity -
7 Dual 8-bit counters PWM mode and Dual 8-bit counters PWM Low mode.
9 compatible: "nxp,flexio-pwm"
11 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 "#pwm-cells":
23 pwm-cells:
24 - channel
[all …]
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | microchip,lan865x.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 LAN865x standalone 10BASE-T1L Ethernet controller with SPI interface.
9 include: [spi-device.yaml, ethernet-controller.yaml]
12 tx-cut-through-mode:
15 rx-cut-through-mode:
18 plca-enable:
21 plca-node-id:
23 description: Specify the PLCA node ID number
24 plca-node-count:
27 plca-burst-count:
[all …]
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_nxp_pint.c | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Based on STM32 EXTI driver, which is (c) 2016 Open-RnD Sp. z o.o. */
25 uint8_t pin: 6; member
34 /* Tracks pint interrupt source selected for each pin */
37 #define PIN_TO_INPUT_MUX_CONNECTION(pin) \ argument
38 ((PINTSEL_PMUX_ID << PMUX_SHIFT) + (pin))
40 /* Attaches pin to PINT IRQ slot using INPUTMUX */
41 static void attach_pin_to_pint(uint8_t pin, uint8_t pint_slot) in attach_pin_to_pint() argument
45 /* Three parameters here- INPUTMUX base, the ID of the PINT slot, in attach_pin_to_pint()
46 * and a integer describing the GPIO pin. in attach_pin_to_pint()
[all …]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
36 ID 1 2 GND
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
47 compatible: "atmel-xplained-pro-header"
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