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/Zephyr-Core-3.5.0/dts/bindings/display/
Dftdi,ft800.yaml15 pclk:
19 The value to divide the main clock by for PCLK. If the
20 typical main clock was 48MHz and this value is 5, the PCLK
27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
28 the rising edge. If it is set to one, PCLK polarity is on
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
38 changes a PCLK clock early and B[7:2] a PCLK clock later,
83 description: Number of PCLK cycles per visible part of horizontal line
89 Number of PCLK cycles before pixels are scanned out for
[all …]
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/sifive-freedom/
Dsoc.h47 /* On FU740, peripherals are clocked by PCLK. */
49 DT_PROP(DT_NODELABEL(pclk), clock_frequency)
Dfu740_clock.c15 BUILD_ASSERT(KHZ(125125) == DT_PROP(DT_NODELABEL(pclk), clock_frequency),
16 "Unsupported PCLK frequency");
60 /* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */ in fu740_clock_init()
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_wwdgt_gd32.c47 * timeout = pclk * INTERNAL_DIVIDER * (2^prescaler_exp) * (count + 1)
49 * count = (timeout * pclk / INTERNAL_DIVIDER * (2^prescaler_exp) ) - 1
57 uint32_t pclk; in gd32_wwdgt_calc_ticks() local
61 &pclk); in gd32_wwdgt_calc_ticks()
63 return ((timeout * pclk) in gd32_wwdgt_calc_ticks()
Dwdt_dw.h66 #define RPL_PCLK_CYCLES2 0x0 /* 2 pclk cycles */
67 #define RPL_PCLK_CYCLES4 0x1 /* 4 pclk cycles */
68 #define RPL_PCLK_CYCLES8 0x2 /* 8 pclk cycles */
69 #define RPL_PCLK_CYCLES16 0x3 /* 16 pclk cycles */
70 #define RPL_PCLK_CYCLES32 0x4 /* 32 pclk cycles */
71 #define RPL_PCLK_CYCLES64 0x5 /* 64 pclk cycles */
72 #define RPL_PCLK_CYCLES128 0x6 /* 128 pclk cycles */
73 #define RPL_PCLK_CYCLES256 0x7 /* 256 pclk cycles */
341 * @param pclk_cycles Reset pulse length selector (2 to 256 pclk cycles)
/Zephyr-Core-3.5.0/drivers/misc/ft8xx/
Dft8xx.c43 uint8_t pclk; member
55 .pclk = DT_INST_PROP(0, pclk),
165 ft8xx_wr8(FT800_REG_PCLK, config->pclk); in ft8xx_init()
/Zephyr-Core-3.5.0/boards/shields/ftdi_vm800c/
Dftdi_vm800c.overlay21 pclk = <5>;
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_b91.c31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1; in pwm_b91_init()
106 *cycles = sys_clk.pclk * 1000 * 1000 / (reg_pwm_clkdiv + 1); in pwm_b91_get_cycles_per_sec()
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_pl022.c269 #define MAX_FREQ_CONTROLLER_MODE(cfg) (cfg->pclk / 2)
270 #define MAX_FREQ_PERIPHERAL_MODE(cfg) (cfg->pclk / 12)
274 const uint32_t pclk; member
304 static inline uint32_t spi_pl022_calc_prescale(const uint32_t pclk, const uint32_t baud) in spi_pl022_calc_prescale() argument
310 if (pclk < (prescale + 2) * CPSDVR_MAX * baud) { in spi_pl022_calc_prescale()
318 static inline uint32_t spi_pl022_calc_postdiv(const uint32_t pclk, in spi_pl022_calc_postdiv() argument
324 if (pclk / (prescale * (postdiv - 1)) > baud) { in spi_pl022_calc_postdiv()
376 prescale = spi_pl022_calc_prescale(cfg->pclk, spicfg->frequency); in spi_pl022_configure()
377 postdiv = spi_pl022_calc_postdiv(cfg->pclk, spicfg->frequency, prescale); in spi_pl022_configure()
970 .pclk = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency), \
/Zephyr-Core-3.5.0/drivers/serial/
Duart_b91.c140 static void uart_b91_cal_div_and_bwpc(uint32_t baudrate, uint32_t pclk, in uart_b91_cal_div_and_bwpc() argument
149 primeInt = pclk / baudrate; in uart_b91_cal_div_and_bwpc()
150 primeDec = 10 * pclk / baudrate - 10 * primeInt; in uart_b91_cal_div_and_bwpc()
284 uart_b91_cal_div_and_bwpc(cfg->baudrate, sys_clk.pclk * 1000 * 1000, &divider, &bwpc); in uart_b91_configure()
326 uart_b91_cal_div_and_bwpc(cfg->baud_rate, sys_clk.pclk * 1000 * 1000, &divider, &bwpc); in uart_b91_driver_init()
Duart_ns16550.c398 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk) argument
405 if ((baud_rate != 0U) && (pclk != 0U)) {
408 * (uint32_t)(pclk / (16.0 * baud_rate) + 0.5)
410 divisor = ((pclk + (baud_rate << 3))
432 uint32_t pclk = 0U; local
475 pclk = dev_cfg->sys_clk_freq;
484 &pclk) != 0) {
490 set_baud_rate(dev, cfg->baudrate, pclk);
1127 uint32_t mdc, chg, pclk = 0U; local
1131 pclk = dev_cfg->sys_clk_freq;
[all …]
Duart_lpc11u6x.c82 uint32_t pclk; in lpc11u6x_uart0_config_baudrate() local
90 &pclk); in lpc11u6x_uart0_config_baudrate()
91 mul = pclk / (pclk % LPC11U6X_UART0_CLK); in lpc11u6x_uart0_config_baudrate()
93 dl = pclk / (16 * baudrate + 16 * baudrate / mul); in lpc11u6x_uart0_config_baudrate()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/telink_b91/
Dsoc.c82 /* clocks init: CCLK, HCLK, PCLK */ in soc_b91_init()
/Zephyr-Core-3.5.0/dts/arm64/fvp/
Dfvp-aemv8r.dtsi53 uartclk: apb-pclk {
/Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c92 zassert_true((r == 0), "Could not get SPI pclk freq"); in ZTEST()
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_gd32_timer.c431 uint32_t pclk; in counter_gd32_timer_init() local
436 (clock_control_subsys_t)&cfg->clkid, &pclk); in counter_gd32_timer_init()
438 data->freq = pclk / (cfg->prescaler + 1); in counter_gd32_timer_init()
Dcounter_andes_atcpit100.c131 /* Channel 0 ~ 3, 32 bits timer, PCLK source */ in counter_atcpit100_init()
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dst,stm32-rcc.yaml64 'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_b91.c69 i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * i2c_speed))); in i2c_b91_configure()
/Zephyr-Core-3.5.0/boards/arm64/fvp_base_revc_2xaemv8a/
Dfvp_base_revc_2xaemv8a.dts73 uartclk: apb-pclk {
/Zephyr-Core-3.5.0/dts/arm64/qemu/
Dqemu-virt-a53.dtsi55 uartclk: apb-pclk {
Dqemu-virt-arm64.dtsi55 uartclk: apb-pclk {
/Zephyr-Core-3.5.0/dts/riscv/sifive/
Driscv64-fu740.dtsi23 pclk: p-clk { label
/Zephyr-Core-3.5.0/dts/arm/ambiq/
Dambiq_apollo4p.dtsi9 uartclk: apb-pclk {
Dambiq_apollo4p_blue.dtsi9 uartclk: apb-pclk {

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