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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dmikro-bus.yaml15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
Dti,boosterpack-header.yaml14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
/Zephyr-Core-3.5.0/include/zephyr/arch/common/
Dffs.h25 * numbered starting at 1 from the least significant bit. A return value of
47 * numbered starting at 1 from the least significant bit. A return value of
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
Dsoc_port.c22 * even numbered pin goes in the bits 0..3 and the odd in soc_port_pinmux_set()
23 * numbered pin in bits 4..7. in soc_port_pinmux_set()
/Zephyr-Core-3.5.0/scripts/native_simulator/common/src/
Dnsi_internal.h22 * numbered starting at 1 from the least significant bit. A return value of
/Zephyr-Core-3.5.0/tests/benchmarks/sched/
DREADME.rst20 between each numbered step and for the whole cycle, and a running
/Zephyr-Core-3.5.0/subsys/logging/
DKconfig.template.log_format_config35 # Example : LOG_BACKEND_XXX_OUTPUT_TEXT should be numbered 0 across all backends
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Despressif,esp32-pcnt.yaml11 The ESP32's PCNT module has 8 independent counting “units” numbered from 0 to 7.
12 ESP32S2 and ESP32S3 have 4 independent counting “units” numbered from 0 to 3.
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnuvoton,numicro-pinctrl.yaml8 and each numbered subgroup in the pin group defines all the pins for that
Dopenisa,rv32m1-pinctrl.yaml9 and each numbered subgroup in the pin group defines all the pins for that
Dnxp,kinetis-pinctrl.yaml8 and each numbered subgroup in the pin group defines all the pins for that
Dnxp,rt-iocon-pinctrl.yaml8 Each numbered subgroup represents pins with shared configuration for that
Dnxp,s32k3-pinctrl.yaml11 and each numbered subgroup in the pin group defines all the pins for that
Dnxp,lpc-iocon-pinctrl.yaml7 pin configuration defines a peripheral's pin configuration. Each numbered
Dnxp,s32ze-pinctrl.yaml11 and each numbered subgroup in the pin group defines all the pins for that
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_adc.h13 /* Eight ADC channels numbered 0 - 7 */
/Zephyr-Core-3.5.0/tests/benchmarks/sched/src/
Dmain.c28 * between each numbered step and for the whole cycle, and a running
/Zephyr-Core-3.5.0/doc/contribute/documentation/
Dguidelines.rst81 For numbered lists
91 1. This is a new numbered list. If the wasn't a blank line before it,
95 a. This is a numbered list using alphabetic list headings
478 1. And for numbered list items, the continuation
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_xlnx_gem_priv.h552 /* The values of this enum are consecutively numbered */
567 /* The values of this enum are consecutively numbered */
582 /* The values of this enum are consecutively numbered */
604 /* The values of this enum are consecutively numbered */
/Zephyr-Core-3.5.0/arch/xtensa/core/
DREADME-WINDOWS.rst96 By convention spill regions always store the lowest numbered register
/Zephyr-Core-3.5.0/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/
Dmain.c150 /* Djkstra's solution: always pick up the lowest numbered fork first */ in philosopher()
/Zephyr-Core-3.5.0/samples/kernel/metairq_dispatch/
DREADME.rst35 * On average, higher priority (lower numbered) threads have better
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_dw_ace.c22 * controller with 28 lines instantiated. They get numbered
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_stm32g0x.c205 * "physical" pages are numbered starting with 0 on bank1 and 256 on bank2.
/Zephyr-Core-3.5.0/samples/subsys/portability/cmsis_rtos_v2/philosophers/src/
Dmain.c175 /* Djkstra's solution: always pick up the lowest numbered fork first */ in philosopher()

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