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/Zephyr-Core-3.5.0/tests/kernel/mem_heap/shared_multi_heap/boards/
Dmps2_an521.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
8 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11 /delete-node/ memory@38000000;
14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "SSRAM2_3";
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES0";
23 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
27 compatible = "zephyr,memory-region", "mmio-sram";
[all …]
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
8 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 compatible = "zephyr,memory-region", "mmio-sram";
15 zephyr,memory-region = "RES0";
16 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES1";
23 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
27 compatible = "zephyr,memory-region", "mmio-sram";
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h573Xi.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "zephyr,memory-region", "mmio-sram";
13 zephyr,memory-region = "SRAM1";
17 compatible = "zephyr,memory-region", "mmio-sram";
19 zephyr,memory-region = "SRAM2";
23 compatible = "zephyr,memory-region", "mmio-sram";
25 zephyr,memory-region = "SRAM3";
29 flash-controller@40022000 {
Dstm32h563Xi.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
24 compatible = "zephyr,memory-region", "mmio-sram";
26 zephyr,memory-region = "SRAM3";
30 flash-controller@40022000 {
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_lpc55S06_ns.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 sram: sram@400000 { label
22 compatible = "zephyr,memory-region", "mmio-sram";
24 zephyr,memory-region = "SRAMX";
36 compatible = "mmio-sram";
Dnxp_k8xfn256vxx15.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 /* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
14 * Cortex-M4 architecture. For clarity and to avoid the temptation for
18 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
21 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "SRAML";
27 compatible = "mmio-sram";
34 compatible = "soc-nv-flash";
36 erase-block-size = <DT_SIZE_K(4)>;
37 write-block-size = <4>;
Dnxp_ke1xf256vlx16.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 /* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
14 * Cortex-M4 architecture. For clarity and to avoid the temptation for
18 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
21 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "SRAML";
27 compatible = "mmio-sram";
34 compatible = "soc-nv-flash";
36 erase-block-size = <DT_SIZE_K(4)>;
37 write-block-size = <8>;
Dnxp_ke1xf512vlx16.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 /* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
14 * Cortex-M4 architecture. For clarity and to avoid the temptation for
18 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
21 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "SRAML";
27 compatible = "mmio-sram";
34 compatible = "soc-nv-flash";
36 erase-block-size = <DT_SIZE_K(4)>;
37 write-block-size = <8>;
/Zephyr-Core-3.5.0/tests/lib/devicetree/api_ext/
Dapp.overlay5 * SPDX-License-Identifier: Apache-2.0
10 * with real-world devicetree nodes, to allow these tests to run on
16 #address-cells = < 0x1 >;
17 #size-cells = < 0x1 >;
19 test_sram1: sram@20000000 {
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "SRAM_REGION";
24 test_sram2: sram@20001000 {
25 compatible = "zephyr,memory-region", "mmio-sram";
27 zephyr,memory-region = "SRAM@REGION#2";
/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h743.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h750.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h750", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h7a3.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &adc3;
15 compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <16>;
21 erase-block-size = <DT_SIZE_K(8)>;
23 max-erase-time = <3>;
[all …]
Dstm32h745.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
[all …]
/Zephyr-Core-3.5.0/boards/riscv/neorv32/
Dneorv32.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
23 zephyr,sram = &dmem;
25 zephyr,shell-uart = &uart0;
26 zephyr,uart-pipe = &uart0;
31 compatible = "soc-nv-flash", "mmio-sram";
36 compatible = "soc-nv-flash", "mmio-sram";
41 compatible = "mmio-sram";
47 compatible = "gpio-leds";
71 clock-frequency = <DT_FREQ_M(100)>;
[all …]
/Zephyr-Core-3.5.0/tests/drivers/syscon/boards/
Dqemu_cortex_a53.overlay2 * SPDX-License-Identifier: Apache-2.0
8 compatible = "mmio-sram";
13 compatible = "zephyr,memory-region", "mmio-sram";
15 zephyr,memory-region = "RES";
23 reg-io-width = <1>;
/Zephyr-Core-3.5.0/dts/xtensa/nxp/
Dnxp_imx8.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx6";
24 compatible = "mmio-sram";
30 compatible = "mmio-sram";
/Zephyr-Core-3.5.0/samples/drivers/mbox/boards/
Dadp_xc7k_ae350.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * shared memory reserved for the inter-processor communication
12 zephyr,sram = &sram;
15 sram: memory@0 {
16 compatible = "mmio-sram";
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32l23x/
Dgd32l233rc.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "mmio-sram";
18 sram: memory@20000000 { label
19 compatible = "mmio-sram";
24 compatible = "gd,gd32-usart";
43 max-erase-time-ms = <1200>;
44 page-size = <DT_SIZE_K(4)>;
/Zephyr-Core-3.5.0/dts/arm/infineon/
Dxmc4500_F100x1024.dtsi5 * SPDX-License-Identifier: Apache-2.0
13 compatible = "mmio-sram";
18 compatible = "mmio-sram";
23 compatible = "mmio-sram";
32 pages-count = <8>;
33 pages-size = <DT_SIZE_K(16)>;
36 pages-count = <1>;
37 pages-size = <DT_SIZE_K(128)>;
40 pages-count = <3>;
41 pages-size = <DT_SIZE_K(256)>;
[all …]
Dxmc4700_F144x2048.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
17 compatible = "mmio-sram";
22 compatible = "mmio-sram";
31 pages-count = <8>;
32 pages-size = <DT_SIZE_K(16)>;
35 pages-count = <1>;
36 pages-size = <DT_SIZE_K(128)>;
39 pages-count = <7>;
40 pages-size = <DT_SIZE_K(256)>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/ti/
Dam62x_m4.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4f";
26 compatible = "mmio-sram";
27 reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */
31 compatible = "mmio-sram";
32 reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */
[all …]
/Zephyr-Core-3.5.0/dts/xtensa/
Ddc233c.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "cdns,tensilica-xtensa-lx3";
27 compatible = "mmio-sram";
37 compatible = "mmio-sram";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "simple-bus";
/Zephyr-Core-3.5.0/dts/bindings/sram/
Dmmio-sram.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Generic on-chip SRAM description
6 compatible: "mmio-sram"
/Zephyr-Core-3.5.0/dts/arm/nuvoton/
Dnpcx7m6fb.dtsi4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "mmio-sram";
26 compatible = "mmio-sram";
30 soc-id {
31 device-id = <0x21>;
39 compatible ="nuvoton,npcx-fiu-nor";
45 qspi-flags = <NPCX_QSPI_SW_CS1>;
46 mapped-addr = <0x64000000>;
47 pinctrl-0 = <&int_flash_sl>;
48 pinctrl-names = "default";
Dnpcx7m6fc.dtsi4 * SPDX-License-Identifier: Apache-2.0
20 compatible = "mmio-sram";
26 compatible = "mmio-sram";
30 soc-id {
31 device-id = <0x29>;
39 compatible ="nuvoton,npcx-fiu-nor";
45 qspi-flags = <NPCX_QSPI_SW_CS1>;
46 mapped-addr = <0x64000000>;
47 pinctrl-0 = <&int_flash_sl>;
48 pinctrl-names = "default";

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