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/Zephyr-Core-3.5.0/tests/kernel/mem_heap/shared_multi_heap/boards/
Dmps2_an521.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
8 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11 /delete-node/ memory@38000000;
13 ssram2_3: memory@38000000 {
14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "SSRAM2_3";
19 res0: memory@38100000 {
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES0";
[all …]
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
8 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
12 res0: memory@42000000 {
13 compatible = "zephyr,memory-region", "mmio-sram";
15 zephyr,memory-region = "RES0";
16 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
19 res1: memory@43000000 {
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES1";
[all …]
/Zephyr-Core-3.5.0/tests/kernel/mem_heap/shared_multi_heap/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/linker/linker-defs.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
22 struct shared_multi_heap_region region; member
28 .region = { \
41 static void smh_reg_map(struct shared_multi_heap_region *region) in smh_reg_map() argument
46 mem_attr = (region->attr == SMH_REG_ATTR_CACHEABLE) ? K_MEM_CACHE_WB : K_MEM_CACHE_NONE; in smh_reg_map()
49 z_phys_map(&v_addr, region->addr, region->size, mem_attr); in smh_reg_map()
51 region->addr = (uintptr_t) v_addr; in smh_reg_map()
56 * Given a virtual address retrieve the original memory region that the mapping
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/Zephyr-Core-3.5.0/include/zephyr/linker/
Ddevicetree_regions.h5 * SPDX-License-Identifier: Apache-2.0
7 * Generate memory regions from devicetree nodes.
18 * @brief Get the linker memory-region name in a token form
20 * This attempts to use the zephyr,memory-region property (with
21 * non-alphanumeric characters replaced with underscores) returning a token.
28 * sram1: memory@2000000 {
29 * zephyr,memory-region = "MY_NAME";
31 * sram2: memory@2001000 {
32 * zephyr,memory-region = "MY@OTHER@NAME";
46 * @return the name of the memory memory region the node will generate
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/Zephyr-Core-3.5.0/include/zephyr/mem_mgmt/
Dmem_attr.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Memory-Attr Interface
12 * @defgroup memory_attr_interface Memory-Attr Interface
19 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
38 * `zephyr,memory-attr`
41 * with the `zephyr,memory-attr` property. The macro is expanded once for each
51 * @brief memory-attr region structure.
53 * This structure represents the data gathered from DT about a memory-region
54 * marked with memory attributes.
57 /** Memory node full name */
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/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h573Xi.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 sram1: memory@20000000 {
11 compatible = "zephyr,memory-region", "mmio-sram";
13 zephyr,memory-region = "SRAM1";
16 sram2: memory@20040000 {
17 compatible = "zephyr,memory-region", "mmio-sram";
19 zephyr,memory-region = "SRAM2";
22 sram3: memory@20050000 {
23 compatible = "zephyr,memory-region", "mmio-sram";
25 zephyr,memory-region = "SRAM3";
[all …]
Dstm32h563Xi.dtsi5 * SPDX-License-Identifier: Apache-2.0
11 sram1: memory@20000000 {
12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
17 sram2: memory@20040000 {
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
23 sram3: memory@20050000 {
24 compatible = "zephyr,memory-region", "mmio-sram";
26 zephyr,memory-region = "SRAM3";
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/Zephyr-Core-3.5.0/dts/bindings/reserved-memory/
Dmemory-region.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Memory region nodes may be referenced by other device nodes
5 # by adding a memory-region property to the device node.
8 memory-regions:
9 type: phandle-array
10 description: List of memory region phandles
12 memory-region-names:
13 type: string-array
14 description: A list of names, one for each corresponding phandle in memory-region
/Zephyr-Core-3.5.0/doc/services/mem_mgmt/
Dindex.rst3 Memory Attributes
6 It is possible in the devicetree to mark the memory regions with attributes by
7 using the ``zephyr,memory-attr`` property. This property and the related memory
8 region can then be retrieved at run-time by leveraging a provided helper
12 and explained in :zephyr_file:`include/zephyr/dt-bindings/memory-attr/memory-attr.h`.
14 For example, to mark a memory region in the devicetree as non-volatile, cacheable,
15 out-of-order:
17 .. code-block:: devicetree
19 mem: memory@10000000 {
20 compatible = "mmio-sram";
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/Zephyr-Core-3.5.0/include/zephyr/multi_heap/
Dshared_multi_heap.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public API for Shared Multi-Heap framework
28 * @brief Shared Multi-Heap (SMH) interface
29 * @defgroup shared_multi_heap Shared multi-heap interface
33 * The shared multi-heap manager uses the multi-heap allocator to manage a set
34 * of memory regions with different capabilities / attributes (cacheable,
35 * non-cacheable, etc...).
37 * All the different regions can be added at run-time to the shared multi-heap
39 * can be used by drivers or applications to request memory with certain
44 * - At boot time some platform code initialize the shared multi-heap
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/Zephyr-Core-3.5.0/include/zephyr/drivers/mm/
Dsystem_mm.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Memory Management Driver APIs
11 * This contains APIs for a system-wide memory management
27 * @brief Memory Management Driver APIs
28 * @defgroup mm_drv_apis Memory Management Driver APIs
40 /** Write-through caching */
43 /** Full write-back caching */
47 #define SYS_MM_MEM_CACHE_MASK (BIT(3) - 1)
50 * Region permission attributes.
51 * Default should be read-only, no user, no exec.
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/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h7a3.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &adc3;
15 compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <16>;
21 erase-block-size = <DT_SIZE_K(8)>;
23 max-erase-time = <3>;
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Dstm32h743.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
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Dstm32h750.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h750", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Dcoredump.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for coredump pseudo-device driver
23 * @brief Coredump pseudo-device driver APIs
24 * @defgroup coredump_device_interface Coredump pseudo-device driver APIs
30 * @brief Structure describing a region in memory that may be
35 * of memory regions to be captured
38 /** Node of single-linked list, do not modify */
41 /** Address of start of memory region */
44 /** Size of memory region */
53 * @param dump_area_size Size of available memory at dump_area
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/Zephyr-Core-3.5.0/samples/subsys/ipc/openamp/boards/
Dmimxrt1170_evkb_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
15 * Define a subset of the OCRAM2 region for demo to use
16 * Note that shared memory must have specific MPU attributes set.
18 ocram2_overlay: memory@202c0000{
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region="OCRAM2_OVERLAY";
22 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
Dmimxrt1160_evk_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
15 * Define a subset of the OCRAM2 region for demo to use
16 * Note that shared memory must have specific MPU attributes set.
18 ocram2_overlay: memory@202c0000{
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region="OCRAM2_OVERLAY";
22 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
Dmimxrt1170_evk_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
15 * Define a subset of the OCRAM2 region for demo to use
16 * Note that shared memory must have specific MPU attributes set.
18 ocram2_overlay: memory@202c0000{
19 compatible = "zephyr,memory-region", "mmio-sram";
21 zephyr,memory-region="OCRAM2_OVERLAY";
22 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
/Zephyr-Core-3.5.0/include/zephyr/debug/
Dgdbstub.h4 * SPDX-License-Identifier: Apache-2.0
18 /* Access permissions for memory regions */
29 /** Describe one memory region */
31 /** Start address of a memory region */
34 /** End address of a memory region */
37 /** Memory region attributes */
45 * Memory region descriptions used for GDB memory access.
47 * This array specifies which region of memory GDB can access
49 * memory read/write in GDB stub to memory that can be
50 * legally accessed without resulting in memory faults.
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/Zephyr-Core-3.5.0/doc/services/ipc/ipc_service/backends/
Dipc_service_icmsg.rst8 memory footprint. The ICMsg backend is build on top of :ref:`spsc_pbuf`.
13 The ICMsg backend uses shared memory and MBOX devices for exchanging data.
14 Shared memory is used to store the data, MBOX devices are used to signal that
27 * Define two memory regions and assign them to ``tx-region`` and ``rx-region``
28 of an instance. Ensure that the memory regions used for data exchange are
29 unique (not overlapping any other region) and accessible by both domains
37 .. code-block:: devicetree
39 reserved-memory {
40 tx: memory@20070000 {
44 rx: memory@20078000 {
[all …]
/Zephyr-Core-3.5.0/dts/bindings/base/
Dzephyr,memory-region.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Compatible for devices resulting in linker memory regions
6 compatible: "zephyr,memory-region"
8 include: [base.yaml, "zephyr,memory-attr.yaml"]
11 zephyr,memory-region:
16 memory region in the final executable. The region address and size
/Zephyr-Core-3.5.0/include/zephyr/kernel/
Dthread_stack.h4 * SPDX-License-Identifier: Apache-2.0
39 * stack buffer region with guard areas that trigger a MPU or MMU fault
63 * to the CPU and ABI requirements. This is not used for any memory protection
79 * all the data members that are pre-populated in arch_new_thread().
89 (type *)((ptr) - sizeof(type))
122 * @param size Size of the stack memory region
136 * @param size Size of the stack memory region
150 * @param size Size of the stack memory region
157 * @brief Define a toplevel kernel stack memory region in specified section
159 * This defines a region of memory for use as a thread stack in
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/Zephyr-Core-3.5.0/tests/subsys/mem_mgmt/mem_attr/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 const struct mem_attr_region_t *region; in ZTEST() local
16 num_regions = mem_attr_get_regions(&region); in ZTEST()
23 if (region[idx].dt_size == 0x1000) { in ZTEST()
24 zassert_equal(region[idx].dt_addr, 0x10000000, "Wrong region address"); in ZTEST()
25 zassert_equal(region[idx].dt_size, 0x1000, "Wrong region size"); in ZTEST()
26 zassert_equal(region[idx].dt_attr, DT_MEM_ARM_MPU_FLASH | in ZTEST()
28 "Wrong region address"); in ZTEST()
29 zassert_true((strcmp(region[idx].dt_name, "memory@10000000") == 0), in ZTEST()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/sys/
Dmem_manage.h4 * SPDX-License-Identifier: Apache-2.0
17 * @brief Memory Management
18 * @defgroup memory_management Memory Management
31 /** Write-through caching. Used by certain drivers. */
34 /** Full write-back caching. Any RAM mapped wants this. */
43 #define K_MEM_CACHE_MASK (BIT(3) - 1)
46 * Region permission attributes. Default is read-only, no user, no exec
49 /** Region will have read/write access (and not read-only) */
52 /** Region will be executable (normally forbidden) */
55 /** Region will be accessible to user mode (normally supervisor-only) */
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/Zephyr-Core-3.5.0/soc/arm/nxp_imx/mimx8ml8_m7/
Dmpu_regions.c4 * SPDX-License-Identifier: Apache-2.0
23 * Region 0 [0x0000_0000 - 0x4000_0000]:
24 * Memory with Device type, not executable, not shareable, non-cacheable.
31 * Region 1 ITCM[0x0000_0000 - 0x0001_FFFF]:
32 * Memory with Normal type, not shareable, non-cacheable
39 * Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]:
40 * Memory with Normal type, not shareable, cacheable
47 * Region 3 DTCM[0x2000_0000 - 0x2002_0000]:
48 * Memory with Normal type, not shareable, non-cacheable
55 * Region 4 DDR[0x4000_0000 - 0x8000_0000]:
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