Searched full:lcd_clk (Results 1 – 5 of 5) sorted by relevance
340 * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:341 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.345 * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:346 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.350 * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.351 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.355 * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.356 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.370 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without371 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of[all …]
721 * The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:722 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.729 * The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:730 * delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.737 * The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.738 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.745 * The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.746 * 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.758 * The output data bit $n is delayed by module clock LCD_CLK. 0: output without759 * delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of[all …]
37 // lcd_clk = module_clock_src / (n + b / a) in lcd_hal_cal_pclk_freq()38 // pixel_clk = lcd_clk / mo in lcd_hal_cal_pclk_freq()
27 #define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-…28 #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bi…29 #define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width83 // lcd_clk = module_clock_src / (div_num + div_b / div_a) in lcd_ll_set_group_clock_coeff()123 * @param prescale Prescale value, PCLK = LCD_CLK / prescale129 // Formula: pixel_clk = lcd_clk / (1 + clkcnt_n) in lcd_ll_set_pixel_clock_prescale()
560 lcd_clk:
