| /trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/cmsis_core/ |
| D | platform_irq.h | 78 GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
94 GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
110 GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
126 GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
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| /trusted-firmware-m-latest/platform/ext/target/arm/mps3/an524/device/include/ |
| D | platform_irq.h | 91 GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
107 GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
123 GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
139 GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
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| /trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/cmsis_core/ |
| D | platform_irq.h | 102 GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
118 GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
134 GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
150 GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
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| /trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/common/device/include/ |
| D | platform_irq.h | 108 GPIO0_0_IRQn = 73, /* GPIO0 has 16 pins with IRQs */
124 GPIO1_0_IRQn = 89, /* GPIO1 has 16 pins with IRQs */
140 GPIO2_0_IRQn = 105, /* GPIO2 has 16 pins with IRQs */
156 GPIO3_0_IRQn = 121, /* GPIO3 has 4 pins with IRQs */
|
| /trusted-firmware-m-latest/docs/integration_guide/ |
| D | tfm_secure_irq_integration_guide.rst | 71 ``irqs`` attribute of the Secure Partition manifest.
72 ``irqs`` is a list of Interrupt Request (IRQ) assigned to the Secure Partition.
74 Secure Partitions are not allowed to share IRQs with other Secure Partitions.
87 "irqs": [
134 "irqs": [
160 - the FLIH Function for handling ``FLIH`` IRQs provided by Secure Partition:
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/common/device/include/ |
| D | platform_irq.h | 110 GPIO0_0_IRQn = 73, /* GPIO0 has 16 pins with IRQs */
126 GPIO1_0_IRQn = 89, /* GPIO1 has 16 pins with IRQs */
142 GPIO2_0_IRQn = 105, /* GPIO2 has 16 pins with IRQs */
158 GPIO3_0_IRQn = 121, /* GPIO3 has 4 pins with IRQs */
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/device/include/ |
| D | platform_irq.h | 114 GPIO0_0_IRQn = 73, /* GPIO0 has 16 pins with IRQs */
130 GPIO1_0_IRQn = 89, /* GPIO1 has 16 pins with IRQs */
146 GPIO2_0_IRQn = 105, /* GPIO2 has 16 pins with IRQs */
162 GPIO3_0_IRQn = 121, /* GPIO3 has 4 pins with IRQs */
|
| /trusted-firmware-m-latest/tools/templates/ |
| D | manifestfilename.template | 35 {% if manifest.irqs %}
36 {% for irq in manifest.irqs %}
|
| D | partition_load_info.template | 39 {% set counter.irq_counter = manifest.irqs|count %}
61 {% for irq in manifest.irqs %}
93 struct irq_load_info_t irqs[{{(manifest.name|upper + "_NIRQS")}}];
256 .irqs = {
257 {% for irq in manifest.irqs %}
|
| /trusted-firmware-m-latest/secure_fw/spm/core/ |
| D | psa_irq_api.c | 68 /* This API is for FLIH IRQs only */ in tfm_spm_partition_psa_reset_signal()
102 /* This API is for SLIH IRQs only */ in tfm_spm_partition_psa_eoi()
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/ |
| D | tfm_interrupts.c | 89 /* CMU_MHU0 is a secure peripheral, so its IRQs have to target S state */ in mailbox_irq_init()
114 /* CMU_MHU1 is a secure peripheral, so its IRQs have to target S state */ in mailbox_irq_1_init()
|
| D | tfm_hal_platform_reset.c | 26 * Disable IRQs to stop all threads, not just the thread that in tfm_hal_system_halt()
|
| /trusted-firmware-m-latest/tools/ |
| D | tfm_parse_manifest_list.py | 39 'stack_size', 'description', 'entry_init', 'heap_size', 'mmio_regions', 'services', 'irqs', 'depend…
106 irq_list = manifest.get('irqs', [])
397 # number (0) when there are no irqs.
399 for irq_idx, irq in enumerate(manifest.get('irqs', [])):
406 logging.debug('{} has {} IRQS'.format(manifest['name'], irq_idx +1))
409 raise Exception('Total number of Services and IRQs of {} exceeds the limit (28)'
|
| /trusted-firmware-m-latest/platform/ext/common/ |
| D | tfm_hal_reset_halt.c | 19 * Disable IRQs to stop all threads, not just the thread that in tfm_hal_system_halt()
|
| /trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/an547/ |
| D | tfm_hal_platform_reset_halt.c | 23 * Disable IRQs to stop all threads, not just the thread that in tfm_hal_system_halt()
|
| /trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/an557/ |
| D | tfm_hal_platform_reset_halt.c | 23 * Disable IRQs to stop all threads, not just the thread that in tfm_hal_system_halt()
|
| /trusted-firmware-m-latest/secure_fw/partitions/ns_agent_mailbox/ |
| D | ns_agent_mailbox.yaml | 22 "irqs": [
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/manifest/ |
| D | ns_agent_mailbox.yaml | 24 "irqs": [
|
| /trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/ |
| D | tfm_hal_platform.c | 73 * Disable IRQs to stop all threads, not just the thread that in tfm_hal_system_halt()
|
| /trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Native_Driver/ |
| D | gfc100_eflash_drv.c | 126 * \brief Enables or disables IRQs
129 * \param[in] irq_mask IRQs to enable/disable
130 * \param[in] enable True if the given IRQs need to be enabled, false
|
| /trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/armclang/ |
| D | startup_psoc64_s.s | 104 CPSID i ; Disable IRQs
|
| /trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/iar/ |
| D | startup_psoc64_s.s | 109 CPSID i ; Disable IRQs
|
| /trusted-firmware-m-latest/platform/ext/target/rpi/rp2350/ |
| D | tfm_hal_multi_core.c | 66 /* Prevent IRQs to fire, as their handlers might be in Flash */ in __not_in_flash_func()
|
| /trusted-firmware-m-latest/platform/ext/target/arm/rse/common/bl2/ |
| D | boot_dma.c | 95 /* Use combined secure interrupt because there are no channel IRQs */ in boot_dma_init_cfg()
|
| /trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/CMSIS_Driver/ |
| D | Driver_GFC100_EFlash.c | 216 * gfc100_eflash_row_write. It has the disadvantage that all IRQs have in ARM_Flashx_ProgramData()
|
