| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | Kconfig.intel_adsp_hda | 4 # SPDX-License-Identifier: Apache-2.0
7 bool "Intel ADSP HDA Host In DMA drivers"
10 depends on DMA
13 Intel ADSP Host HDA DMA driver.
16 bool "Intel ADSP HDA Host Out DMA drivers"
21 Intel ADSP Host HDA DMA driver.
24 bool "Intel ADSP HDA Link In DMA drivers"
29 Intel ADSP Link In HDA DMA driver.
32 bool "Intel ADSP HDA Link Out DMA drivers"
37 Intel ADSP Link Out HDA DMA driver.
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| D | Kconfig.intel_adsp_gpdma | 1 # DMA configuration options
4 # SPDX-License-Identifier: Apache-2.0
11 Intel ADSP DMA driver.
20 dma controller ownership from the host.
34 source "drivers/dma/Kconfig.dw_common"
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| /Zephyr-Core-3.5.0/tests/boards/intel_adsp/hda/src/ |
| D | dma.c | 2 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/dma.h>
39 * Tests host input streams with the DMA API
46 const struct device *dma; in ZTEST() local
70 dma = DEVICE_DT_GET(DT_NODELABEL(hda_host_in)); in ZTEST()
71 zassert_true(device_is_ready(dma), "DMA device is not ready"); in ZTEST()
73 channel = dma_request_channel(dma, NULL); in ZTEST()
74 zassert_true(channel >= 0, "Expected a valid DMA channel"); in ZTEST()
75 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dma channel"); in ZTEST()
78 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "host reset"); in ZTEST()
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| /Zephyr-Core-3.5.0/drivers/sdhc/ |
| D | Kconfig.intel | 2 # SPDX-License-Identifier: Apache-2.0
13 validated using intel's EMMC host controller.
17 bool "EMMC host controller interrupt mode"
20 EMMC host controller interrupt mode support.
23 bool "EMMC host controller DMA mode"
26 EMMC host controller DMA mode support.
29 bool "EMMC host controller ADMA mode"
32 EMMC host controller ADMA mode support.
35 int "EMMC host controller ADMA Descriptor size"
39 EMMC host controller ADMA Descriptor size.
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| D | Kconfig.mcux_sdif | 2 # SPDX -License-Identifier: Apache-2.0
11 Enable the NXP SDIF Host controller driver
16 bool "DMA support for MCUX SDIF driver"
19 Enable DMA support for MCUX SDIF driver. May be disabled to reduce
24 # SDIF DMA needs 32 bit aligned buffers
29 int "Size of DMA descriptor buffer in bytes"
32 Size of MCUX SDIF DMA descriptor buffer in bytes
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| D | Kconfig.imx | 2 # SPDX -License-Identifier: Apache-2.0
12 Enable the NXP IMX SD Host controller driver
23 bool "DMA support for USDHC"
27 Enable DMA support for USDHC
31 # USDHC DMA needs 32 bit aligned buffers
36 int "Size of DMA descriptor buffer in bytes"
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| D | Kconfig | 2 # SPDX-License-Identifier: Apache-2.0
7 Include drivers for SD host controller
27 Some SD host controllers require alignment of their data buffers
28 in order to DMA to work correctly. Devices should change default of
35 Selected by host controller driver if UHS support is present. required
41 Selected by host controller driver if SPI mode support is required.
47 Selected by host controller driver if native SD mode support is
51 module-str = sdhc
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | brcm,iproc-pax-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v1
13 Register space for the memory mapped PAX DMA controller registers,
17 bd-memory:
19 description: Uncached memory address to populate dma buffer descriptors
21 scr-addr-loc:
23 description: Location where address of the scratch buffer host has populated
25 scr-size-loc:
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| D | brcm,iproc-pax-dma-v2.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
6 include: dma-controller.yaml
8 compatible: brcm,iproc-pax-dma-v2
13 Register space for the memory mapped PAX DMA controller registers,
17 bd-memory:
19 description: Uncached memory address to populate dma buffer descriptors
21 scr-addr-loc:
23 description: Location where address of the scratch buffer host has populated
25 scr-size-loc:
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| /Zephyr-Core-3.5.0/dts/xtensa/intel/ |
| D | intel_adsp_cavs.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 lpgpdma0: dma@7c000 {
12 compatible = "intel,adsp-gpdma";
13 #dma-cells = <1>;
17 interrupt-parent = <&cavs_intc3>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
24 lpgpdma1: dma@7d000 {
25 compatible = "intel,adsp-gpdma";
26 #dma-cells = <1>;
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| D | intel_adsp_cavs15.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx4";
19 i-cache-line-size = <64>;
20 d-cache-line-size = <64>;
25 compatible = "cdns,tensilica-xtensa-lx4";
31 compatible = "mmio-sram";
36 compatible = "mmio-sram";
40 sysclk: system-clock {
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| D | intel_adsp_ace15_mtpm.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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| D | intel_adsp_ace20_lnl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/endpoint/ |
| D | pcie_ep.h | 8 * SPDX-License-Identifier: Apache-2.0
23 PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
24 PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
34 HOST_TO_DEVICE, /**< Read from Host */
35 DEVICE_TO_HOST, /**< Write to Host */
50 * interrupt-safe APIS. Registration of callbacks is done via
95 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_read()
97 return api->conf_read(dev, offset, data); in pcie_ep_conf_read()
114 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_write()
116 api->conf_write(dev, offset, data); in pcie_ep_conf_write()
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
37 description: Enable SPI DMA support
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| /Zephyr-Core-3.5.0/include/zephyr/logging/ |
| D | log_backend_adsp_hda.h | 4 * SPDX-License-Identifier: Apache-2.0
15 * When the log is flushed and written with DMA an IPC message should
16 * be sent to inform the host. This hook function pointer allows for that
24 * inform the Host of DMA log data. This hook may be called
28 * @param channel HDA stream (DMA Channel) to use for logging
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| /Zephyr-Core-3.5.0/drivers/pcie/endpoint/ |
| D | pcie_ep_common.c | 2 * SPDX-License-Identifier: Apache-2.0
14 * PCIe writes (posted) have reached Host, i.e. to flush PCIe writes,
22 * As can be seen in the table, for 64-bit systems, we could just do sys_read8
23 * on mapped Host address to generate a dummy PCIe read, before unmapping the
24 * address - irrespective of low/high outbound memory usage as core is capable
28 * For 32-bit systems, if using low outbound memory for memcpy/DMA,
30 * But, for 32-bit systems using high outbound memory for DMA operation,
34 * +-------------+----------------------+-------------------------------------+
36 * +-------------+----------------------+----------------+--------------------+
37 * | 64-bit | | highmem | sys_read8 |
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| /Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 4 * SPDX-License-Identifier: Apache-2.0
7 /* The SPI STM32 backend implements dedicated SPI driver for Host Commands. Unfortunately, the
8 * current SPI API can't be used to handle the host commands communication. The main issues are
9 * unknown command size sent by the host (the SPI transaction sends/receives specific number of
11 * transaction), see https://github.com/zephyrproject-rtos/zephyr/issues/56091.
19 #include <zephyr/drivers/dma/dma_stm32.h>
20 #include <zephyr/drivers/dma.h>
29 * dedicated for Host Commands. It disabled standard SPI driver. For STM32 SPI "st,stm32-spi" has
30 * to be changed to "st,stm32-spi-host-cmd". The remaining "additional" compatible strings should
43 * request, the host will clock in bytes until it sees the framing byte, then
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/ |
| D | esp32s3-xtensa-intmux.h | 4 * SPDX-License-Identifier: Apache-2.0
39 #define SDIO_HOST_INTR_SOURCE 30 /* interrupt of SD/SDIO/MMC HOST, level*/
51 #define SPI2_DMA_INTR_SOURCE 44 /* interrupt of SPI2 DMA, level*/
52 #define SPI3_DMA_INTR_SOURCE 45 /* interrupt of SPI3 DMA, level*/
72 #define DMA_IN_CH0_INTR_SOURCE 66 /* interrupt of general DMA RX channel 0, LEVEL*/
73 #define DMA_IN_CH1_INTR_SOURCE 67 /* interrupt of general DMA RX channel 1, LEVEL*/
74 #define DMA_IN_CH2_INTR_SOURCE 68 /* interrupt of general DMA RX channel 2, LEVEL*/
75 #define DMA_IN_CH3_INTR_SOURCE 69 /* interrupt of general DMA RX channel 3, LEVEL*/
76 #define DMA_IN_CH4_INTR_SOURCE 70 /* interrupt of general DMA RX channel 4, LEVEL*/
77 #define DMA_OUT_CH0_INTR_SOURCE 71 /* interrupt of general DMA TX channel 0, LEVEL*/
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| D | esp32s2-xtensa-intmux.h | 4 * SPDX-License-Identifier: Apache-2.0
50 #define SDIO_HOST_INTR_SOURCE 40 /* SD/SDIO/MMC HOST, level */
67 #define SPI2_DMA_INTR_SOURCE 57 /* SPI2 DMA, level */
68 #define SPI3_DMA_INTR_SOURCE 58 /* interrupt of SPI3 DMA, level */
91 #define PMS_DMA_RX_I_ILG_INTR_SOURCE 81 /* illegal DMA RX access, level */
92 #define PMS_DMA_TX_I_ILG_INTR_SOURCE 82 /* illegal DMA TX access, level */
96 #define DMA_COPY_INTR_SOURCE 84 /* DMA copy, level */
97 #define SPI4_DMA_INTR_SOURCE 85 /* SPI4 DMA, level */
102 #define CRYPTO_DMA_INTR_SOURCE 90 /* encrypted DMA, level */
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | cavs-idc.h | 4 * SPDX-License-Identifier: Apache-2.0
41 * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
61 * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
89 * level 2-5 interrupts). The "mask" field shows the current masking
114 #define CAVS_L2_HPGPDMA BIT(24) /* HP General Purpose DMA */
119 #define CAVS_L2_SHA BIT(16) /* SHA-256 */
122 #define CAVS_L2_HIPC BIT(7) /* Host IPC */
128 #define CAVS_L3_DSPGHOS(n) BIT(16 + n) /* DSP Gateway Host Output Stream */
129 #define CAVS_L3_HPGPDMA BIT(15) /* HP General Purpose DMA */
130 #define CAVS_L3_DSPGHIS(n) BIT(n) /* DSP Gateway Host Input Stream */
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| /Zephyr-Core-3.5.0/doc/services/device_mgmt/ |
| D | ec_host_cmd.rst | 3 EC Host Command
8 The host command protocol defines the interface for a host, or application processor, to
9 communicate with a target embedded controller (EC). The EC Host command subsystem implements the
10 target side of the protocol, generating responses to commands sent by the host. The host command
16 The Host Command subsystem contains a few components:
32 SHI (Serial Host Interface) is different to this because it is used only for communication with a
33 host. SHI does not have API itself, thus the backend and peripheral driver layers are combined into
39 Another case is SPI. Unfortunately, the current SPI API can't be used to handle the host commands
40 communication. The main issues are unknown command size sent by the host (the SPI transaction
44 can be changed in the future once the SPI API is extended to host command needs. Please check `the
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | dma.h | 4 * @brief Public APIs for the DMA drivers.
10 * SPDX-License-Identifier: Apache-2.0
25 * @brief DMA Interface
26 * @defgroup dma_interface DMA Interface
45 * This and higher values are dma controller or soc specific.
46 * Refer to the specified dma driver header file.
65 DMA_CHANNEL_NORMAL, /* normal DMA channel */
69 /* DMA attributes */
79 * @brief DMA block configuration structure.
94 * source_gather_en [ 0 ] - 0-disable, 1-enable.
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| /Zephyr-Core-3.5.0/boards/posix/native_posix/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
16 * The execution of native_posix is decoupled from the underlying host and its
20 * But, native_posix can also be linked if desired to the underlying host,
21 * e.g.:You can use the provided Ethernet TAP driver, or a host BLE controller.
23 * In this case, the no-indeterminism principle is lost. Runs of native_posix
24 * will depend on the host load and the interactions with those real host
103 * This is the actual host process main routine. The Zephyr
108 * and calls the "OS" through a per-case fuzz test entry point.
128 * into two known symbols, triggering an app-visible interrupt, and
143 * "DMA-like" data placed into posix_fuzz_buf/sz in LLVMFuzzerTestOneInput()
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| /Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32s3/ |
| D | esp32s3_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
13 #include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
19 zephyr,flash-controller = &flash;
23 #address-cells = <1>;
24 #size-cells = <0>;
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