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/Zephyr-Core-3.5.0/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
7 include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
22 single-wire:
25 Enable the single wire half-duplex communication.
30 tx-rx-swap:
35 tx-invert:
41 rx-invert:
47 pinctrl-0:
50 pinctrl-names:
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/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Ddevice_power.c5 * SPDX-License-Identifier: Apache-2.0
27 * Some peripherals if enabled always assert their CLK_REQ bits.
41 SCB->SCR &= ~(1ul << 2); in soc_lite_sleep_enable()
42 PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT; in soc_lite_sleep_enable()
47 * a minimum of 3ms to lock. During this time the main clock
52 SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_enable()
53 PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY; in soc_deep_sleep_enable()
57 * Clear PCR Sleep control sleep all causing HW to de-assert all peripheral
60 * peripheral state therefore we force HW to de-assert the SLP_EN signals.
64 PCR_REGS->SYS_SLP_CTRL = 0U; in soc_deep_sleep_disable()
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/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
34 * We touch the Cortex-M's primary mask and base priority registers
70 * to assert SLP_EN to all peripherals on WFI. in z_power_soc_deep_sleep()
74 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
75 pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY; in z_power_soc_deep_sleep()
76 pcr->OSC_ID = pcr->SYS_SLP_CTRL; in z_power_soc_deep_sleep()
87 * PM post ops. This de-asserts peripheral SLP_EN signals. in z_power_soc_deep_sleep()
89 pcr->SYS_SLP_CTRL = 0U; in z_power_soc_deep_sleep()
90 SCB->SCR &= ~BIT(2); in z_power_soc_deep_sleep()
93 htmr0->PRLD = 0U; /* make sure its stopped */ in z_power_soc_deep_sleep()
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Ddevice_power.c5 * SPDX-License-Identifier: Apache-2.0
53 sys_write32(pcr->CLK_REQ[i], vbm_addr); in soc_debug_sleep_clk_req()
57 sys_write32(pcr->SYS_SLP_CTRL, vbm_addr); in soc_debug_sleep_clk_req()
59 sys_write32(ecs->SLP_STS_MIRROR, vbm_addr); in soc_debug_sleep_clk_req()
77 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_en()
78 regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT; in soc_deep_sleep_non_wake_en()
87 regs->GIRQ22.EN_CLR = UINT32_MAX; in soc_deep_sleep_non_wake_dis()
88 regs->GIRQ22.SRC = UINT32_MAX; in soc_deep_sleep_non_wake_dis()
92 /* When MEC172x drivers are power-aware this should be move there */
100 regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT; in soc_deep_sleep_wake_en()
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/Zephyr-Core-3.5.0/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
93 /* Device run time data */
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
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Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
34 /* Device run time data */
57 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
62 return REG8(&regs->RX_FIFO); in rxb_rd8()
86 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
88 regs->MODE = qmode; in qmspi_set_frequency()
128 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
134 regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK)) in qmspi_set_signalling_mode()
147 switch (config->operation & SPI_LINES_MASK) { in qmspi_config_get_lines()
173 * NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
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/Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/src/
Darm_interrupt.c4 * SPDX-License-Identifier: Apache-2.0
13 static volatile int expected_reason = -1;
31 (pEsf->basic.r0 == 0) && in check_esf_matches_expectations()
32 (pEsf->basic.r1 == 1) && in check_esf_matches_expectations()
33 (pEsf->basic.r2 == 2) && in check_esf_matches_expectations()
34 (pEsf->basic.r3 == 3) && in check_esf_matches_expectations()
35 (pEsf->basic.lr == 15) && in check_esf_matches_expectations()
36 (*(uint16_t *)pEsf->basic.pc == expected_fault_instruction); in check_esf_matches_expectations()
39 return -1; in check_esf_matches_expectations()
43 const struct _callee_saved *callee_regs = pEsf->extra_info.callee; in check_esf_matches_expectations()
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/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt5xx/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
32 /* Board System oscillator settling time in us */
184 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
185 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
191 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
211 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in z_arm_platform_init()
250 /* Updated XTAL oscillator settling time */ in clock_init()
277 /* Set up clock selectors - Attach clocks to the peripheries. */ in clock_init()
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/Zephyr-Core-3.5.0/drivers/fpga/
Dfpga_ice40.c4 * SPDX-License-Identifier: Apache-2.0
32 * restore the default pinctrl settings. On some higher-end microcontrollers
36 * However, on lower-end microcontrollers, the amount of time that elapses
38 * leaves us with the bitbanging option. Of course, on lower-end
39 * microcontrollers, the amount of time required to execute something
42 * in order to bitbang on lower-end microcontrollers, we actually require
47 * - FPGA_ICE40_LOAD_MODE_SPI (for higher-end microcontrollers)
48 * - FPGA_ICE40_LOAD_MODE_GPIO (for lower-end microcontrollers)
66 * Values in Hz, intentionally to be comparable with the spi-max-frequency
67 * property from DT bindings in spi-device.yaml.
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-2.1.rst13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-3.0.rst22 * CVE-2021-3835: `Zephyr project bug tracker GHSA-fm6v-8625-99jf
23 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-fm6v-8625-99jf>`_
25 * CVE-2021-3861: `Zephyr project bug tracker GHSA-hvfp-w4h8-gxvj
26 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hvfp-w4h8-gxvj>`_
28 * CVE-2021-3966: `Zephyr project bug tracker GHSA-hfxq-3w6x-fv2m
29 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfxq-3w6x-fv2m>`_
36 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
53 * Added ``ranges`` and ``dma-ranges`` as invalid property to be used with DT_PROP_LEN()
58 CRC-16-ANSI checksum. A new function, :c:func:`crc16_reflect`, has been
69 * The following Kconfig options related to radio front-end modules (FEMs) were
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/Zephyr-Core-3.5.0/drivers/sensor/lis2dh/
Dlis2dh_trigger.c4 * SPDX-License-Identifier: Apache-2.0
24 const struct lis2dh_config *cfg = dev->config; in setup_int1()
26 gpio_pin_interrupt_configure_dt(&cfg->gpio_drdy, in setup_int1()
37 const struct lis2dh_config *cfg = dev->config; in lis2dh_trigger_drdy_set()
38 struct lis2dh_data *lis2dh = dev->data; in lis2dh_trigger_drdy_set()
41 if (cfg->gpio_drdy.port == NULL) { in lis2dh_trigger_drdy_set()
43 return -ENOTSUP; in lis2dh_trigger_drdy_set()
49 atomic_clear_bit(&lis2dh->trig_flags, TRIGGED_INT1); in lis2dh_trigger_drdy_set()
51 status = lis2dh->hw_tf->update_reg(dev, LIS2DH_REG_CTRL3, in lis2dh_trigger_drdy_set()
54 lis2dh->handler_drdy = handler; in lis2dh_trigger_drdy_set()
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/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
146 (struct i2c_xec_data *const) (dev->data); in i2c_ctl_wr()
147 struct i2c_smb_regs *regs = (struct i2c_smb_regs *)cfg->base_addr; in i2c_ctl_wr()
149 data->i2c_ctrl = ctrl; in i2c_ctl_wr()
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/Zephyr-Core-3.5.0/drivers/espi/
Despi_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
40 * length specified is non-zero.
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
77 * ------------------------------------------------------------------------|
79 * ------------------------------------------------------------------------|
81 * ------------------------------------------------------------------------|
88 * ------------------------------------------------------------------------|
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Despi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <assert.h>
14 #include <zephyr/dt-bindings/espi/npcx_espi.h>
31 /* mapping table between eSPI reset signal and wake-up input */
52 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
106 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
110 uint8_t bitmask; /* VW signal bits-mask */
114 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
118 uint8_t bitmask; /* VW signal bits-mask */
123 * npcxn-espi-vws-map.dtsi device tree file for more detail.
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/Zephyr-Core-3.5.0/doc/contribute/coding_guidelines/
Dindex.rst13 but not enforced. Rules are not yet enforced in CI and pull-requests cannot be
33 Coding guideline rules may be removed/changed at any time by filing a
39 The coding guideline rules are based on MISRA-C 2012 and are a subset of MISRA-C.
47 available through the project. If you need a copy of MISRA-C 2012, please
53 .. list-table:: Main rules
54 :header-rows: 1
57 * - MISRA C 2012
58 - Severity
59 - Description
60 - CERT C
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/Zephyr-Core-3.5.0/cmake/modules/
Dextensions.cmake1 # SPDX-License-Identifier: Apache-2.0
14 # 1. Zephyr-aware extensions
21 # 2. Kconfig-aware extensions
23 # 3. CMake-generic extensions
39 # 1. Zephyr-aware extensions
44 # "zephyr". zephyr is a catch-all CMake library for source files that
47 # [0] https://cmake.org/cmake/help/latest/manual/cmake-buildsystem.7.html
61 # As a very high-level introduction here are two call graphs that are
67 # zephyr_library_compile_options() --> target_compile_options()
70 # zephyr_cc_option() ---> target_cc_option()
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/Zephyr-Core-3.5.0/subsys/bluetooth/host/
Dconn.c1 /* conn.c - Bluetooth connection handling */
4 * Copyright (c) 2015-2016 Intel Corporation
6 * SPDX-License-Identifier: Apache-2.0
30 #include "common/assert.h"
73 bt_conn_tx_cb_t cb = tx->cb; in conn_tx_destroy()
74 void *user_data = tx->user_data; in conn_tx_destroy()
81 cb(conn, user_data, -ESHUTDOWN); in conn_tx_destroy()
149 if (conn->type == BT_CONN_TYPE_BR || !bt_dev.le.acl_mtu) { in bt_conn_get_pkts()
158 if (conn->type == BT_CONN_TYPE_ISO) { in bt_conn_get_pkts()
182 return "disconnect-complete"; in state2str()
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/Zephyr-Core-3.5.0/samples/modules/tflite-micro/hello_world/train/
Dtrain_hello_world_model.ipynb31 "<table class=\"tfo-notebook-buttons\" align=\"left\">\n",
36 …o_world_model.ipynb\"><img src=\"https://www.tensorflow.org/images/GitHub-Mark-32px.png\" />View s…
53 "id": "5PYwRFppd-WB"
84 "outputId": "510567d6-300e-40e2-f5b8-c3520a3f3a8b",
97 …"Requirement already satisfied: tensorflow==2.4.0rc0 in /usr/local/lib/python3.6/dist-packages (2.…
98 …"Requirement already satisfied: termcolor~=1.1.0 in /usr/local/lib/python3.6/dist-packages (from t…
99 …"Requirement already satisfied: gast==0.3.3 in /usr/local/lib/python3.6/dist-packages (from tensor…
100 …"Requirement already satisfied: astunparse~=1.6.3 in /usr/local/lib/python3.6/dist-packages (from …
101 …"Requirement already satisfied: absl-py~=0.10 in /usr/local/lib/python3.6/dist-packages (from tens…
102 …"Requirement already satisfied: keras-preprocessing~=1.1.2 in /usr/local/lib/python3.6/dist-packag…
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