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/Zephyr-Core-3.5.0/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
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/Zephyr-Core-3.5.0/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
20 cs-interval:
28 cs-setup-time:
32 Chip select setup time, in serial clock cycles. See the TCSS field in
36 cs-hold-time:
40 Chip select hold time, in serial clock cycles. See the TCSH field in
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1060_evk/
Dmimxrt1060_evk_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &is25wp064;
13 zephyr,flash-controller = &s26ks512s0;
15 zephyr,code-partition = &slot0_partition;
21 ahb-prefetch;
22 ahb-read-addr-opt;
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
26 combination-mode;
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/Zephyr-Core-3.5.0/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-Core-3.5.0/dts/bindings/net/wireless/
Dnordic,nrf21540-fem.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This is a representation of the nRF21540 Radio Front-End module.
8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
11 the FEM and SPI configurations using the spi-if property.
17 compatible = "nordic,nrf-spim";
19 cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
22 my_spi_if: nrf21540-spi@0 {
23 compatible = "nordic,nrf21540-fem-spi";
25 spi-max-frequency = <8000000>;
30 compatible = "nordic,nrf21540-fem";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts2 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1062_fmurt6-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
25 telem4-gps2 = &lpuart5;
29 zephyr,flash-controller = &s26ks512s0;
31 zephyr,code-partition = &slot0_partition;
36 zephyr,shell-uart = &lpuart7;
41 compatible = "gpio-leds";
42 green_led: led-1 {
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1050_evk/
Dmimxrt1050_evk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1050_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/display/panel.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "NXP MIMXRT1050-EVK board";
32 zephyr,shell-uart = &lpuart1;
33 zephyr,flash-controller = &s26ks512s0;
35 zephyr,code-partition = &slot0_partition;
40 /* Micron MT48LC16M16A2B4-6AIT:G */
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/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/
Dflexspi_nor_config.h6 * SPDX-License-Identifier: Apache-2.0
186 /* !< Switch to 0-4-4/0-8-8 mode */
199 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
201 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
203 /* !< [0x008-0x00b] Reserved for future use */
205 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
207 /* !< [0x00d-0x00d] CS hold time, default value: 3 */
209 /* !< [0x00e-0x00e] CS setup time, default value: 3 */
211 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
214 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
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/Zephyr-Core-3.5.0/drivers/adc/
Dadc_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
24 #define ADC_RPI_CHANNEL_NUM (ADC_CS_RROBIN_MSB - ADC_CS_RROBIN_LSB + 1)
58 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in adc_start_once()
63 return (uint16_t)adc_hw->result; in adc_get_result()
68 return (adc_hw->cs & ADC_CS_ERR_BITS) ? true : false; in adc_get_err()
74 hw_set_bits(&adc_hw->fcs, ADC_FCS_OVER_BITS); in adc_clear_errors()
75 hw_set_bits(&adc_hw->fcs, ADC_FCS_UNDER_BITS); in adc_clear_errors()
76 hw_set_bits(&adc_hw->fcs, ADC_FCS_ERR_BITS); in adc_clear_errors()
77 hw_set_bits(&adc_hw->cs, ADC_CS_ERR_STICKY_BITS); in adc_clear_errors()
82 adc_hw->cs = ADC_CS_EN_BITS; in adc_enable()
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/Zephyr-Core-3.5.0/doc/build/dts/
Dbindings-upstream.rst1 .. _dt-writing-bindings:
21 Zephyr aims for devicetree :ref:`dt-source-compatibility`. Therefore, if there
24 justify any Zephyr-specific divergences.
28 - There is an existing binding in the mainline Linux kernel. See
32 - Your hardware vendor provides an official binding outside of the Linux
49 - For example, a binding for compatible ``vnd,foo`` must be named ``vnd,foo.yaml``.
50 - If the binding is bus-specific, you can append the bus to the file name;
51 for example, if the binding YAML has ``on-bus: bar``, you may name the file
52 ``vnd,foo-bar.yaml``.
57 All recommendations in :ref:`dt-bindings-default` are requirements when
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/Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/
Dmimxrt595_evk_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
34 zephyr,flash-controller = &mx25um51345g;
36 zephyr,code-partition = &slot0_partition;
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/Zephyr-Core-3.5.0/tests/boards/mec172xevb_assy6906/qspi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
210 * - Find spi device
211 * - Read flash jedec id
248 * - write enable
249 * - erase data in flash device
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/Zephyr-Core-3.5.0/drivers/espi/
Despi_saf_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
62 * Hold off suspend for this interval if erase or program in 32KHz periods.
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
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Despi_saf_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
44 * Delay before first Poll-1 command after suspend in 20 ns units
45 * Hold off suspend for this interval if erase or program in 32KHz periods.
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
82 if (cs == 0) { in mchp_saf_poll2_mask_wr()
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
25 #include <zephyr/dt-bindings/spi/spi.h>
68 * Whatever data is transmitted is looped-back to the receiving buffer of
105 /* Requests - if possible - to keep CS asserted after the transaction */
114 /* Active high logic on CS - Usually, and by default, CS logic is active
118 * the CS control to a gpio line through struct spi_cs_control would be
129 * Default is single, which is the case most of the time.
144 * This can be used to control a CS line via a GPIO line, instead of
145 * using the controller inner CS logic.
150 * GPIO devicetree specification of CS GPIO.
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/Zephyr-Core-3.5.0/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
35 * * Some devices support a Deep Power-Down mode which reduces current
46 * deep-power-down mode.
73 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
75 /* Build-time data associated with the device. */
95 /* Expected JEDEC ID, from jedec-id property */
99 /* Optional support for entering 32-bit address mode. */
104 /* Length of BFP structure, in 32-bit words. */
108 * (little-endian stored words), from sfdp-bfp property
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Dnrf_qspi_nor.c2 * Copyright (c) 2019-2021, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
73 "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
80 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
116 INST_0_SCK_FREQUENCY) - 1)
128 INST_0_SCK_FREQUENCY) - 1)
166 … "Driver only supports NONE, S1B6, S2B1v1, S2B1v4, S2B1v5 or S2B1v6 for quad-enable-requirements");
194 * If no data to transmit/receive - pass 0.
205 * @param op_code is a command value (i.e 0x9F - get Jedec ID)
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/Zephyr-Core-3.5.0/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
93 /* Device run time data */
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
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Dspi_pw.c3 * SPDX-License-Identifier: Apache-2.0
46 return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx); in is_spi_transfer_ongoing()
131 uint8_t dfs = SPI_WORD_SIZE_GET(config->operation); in spi_pw_get_frame_size()
136 LOG_WRN("Unsupported dfs, 1-byte size will be used"); in spi_pw_get_frame_size()
145 struct spi_pw_data *spi = dev->data; in spi_pw_cs_ctrl_enable()
148 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
150 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
151 spi_context_cs_control(&spi->ctx, true); in spi_pw_cs_ctrl_enable()
154 if (spi->cs_mode == CS_SW_MODE) { in spi_pw_cs_ctrl_enable()
156 } else if (spi->cs_mode == CS_GPIO_MODE) { in spi_pw_cs_ctrl_enable()
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/Zephyr-Core-3.5.0/samples/drivers/espi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
242 spi_cfg.cs.delay = 0; in spi_saf_init()
243 spi_cfg.cs.gpio.pin = 0; in spi_saf_init()
244 spi_cfg.cs.gpio.dt_flags = 0; in spi_saf_init()
245 spi_cfg.cs.gpio.port = NULL; in spi_saf_init()
269 return -1; in spi_saf_init()
300 * SAF test requires SPI flash quad enabled so the WP#/HOLD# signals in spi_saf_init()
414 return -1; in spi_saf_init()
448 limit = pr->start + pr->size - 1U; in pr_check_range()
451 if (regs->SAF_PROT_RG[pr->pr_num].START != (pr->start >> 12)) { in pr_check_range()
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/Zephyr-Core-3.5.0/drivers/sdhc/
Dsdhc_spi.c4 * SPDX-License-Identifier: Apache-2.0
133 const struct sdhc_spi_config *config = dev->config; in sdhc_spi_init_card()
134 struct sdhc_spi_data *data = dev->data; in sdhc_spi_init_card()
135 struct spi_config *spi_cfg = data->spi_cfg; in sdhc_spi_init_card()
138 if (spi_cfg->frequency == 0) { in sdhc_spi_init_card()
140 spi_cfg->frequency = SDMMC_CLOCK_400KHZ; in sdhc_spi_init_card()
142 /* the initial 74 clocks must be sent while CS is high */ in sdhc_spi_init_card()
143 spi_cfg->operation |= SPI_CS_ACTIVE_HIGH; in sdhc_spi_init_card()
144 ret = sdhc_spi_rx(config->spi_dev, spi_cfg, data->scratch, 10); in sdhc_spi_init_card()
146 spi_cfg->operation &= ~SPI_CS_ACTIVE_HIGH; in sdhc_spi_init_card()
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.1.rst61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
249 newly created informational-only callback struct :c:struct:`bt_conn_auth_info_cb`.
[all …]
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
[all …]
Drelease-notes-2.5.rst27 * CVE-2021-3323: Under embargo until 2021-04-14
28 * CVE-2021-3321: Under embargo until 2021-04-14
29 * CVE-2021-3320: Under embargo until 2021-04-14
39 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
56 * Changed vcnl4040 dts binding default for property 'proximity-trigger'.
63 * The :c:func:`mqtt_keepalive_time_left` function now returns -1 if keep alive
67 timeout usage must use the new-style k_timeout_t type and not the
87 GPIO-only regulators a devicetree property ``supply-gpios`` is defined as a
101 * ARM Musca-A board and SoC support deprecated and planned to be removed in 2.6.0.
146 sys_heap/k_heaps. Note that the new-style heap is a general
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