| /Zephyr-latest/dts/bindings/misc/ |
| D | nordic,split-channels.yaml | 8 Nordic Split Channels
13 owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
14 child-owned-channels = <7 8 9 10 11>;
16 Which means that channels 0-11 will be assigned to the particular CPU.
18 In addition, `child-owned-channels` property allows to use channels
20 subprocessor(s) assigned, the `child-owned-channels` property
24 owned-channels:
27 List of channels in a split-ownership peripheral that are to be owned
30 nonsecure-channels:
33 List of channels in a split-ownership, split-security peripheral that
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| D | nordic,nrf-dppic-links.yaml | 7 source-channels:
10 Channels that are linked to channels of DPPIC instances on separate
13 sink-channels:
16 Channels that are linked to channels of DPPIC instances on separate
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| /Zephyr-latest/soc/nordic/nrf53/ |
| D | sync_rtc.c | 71 * @param channels Details about channels
74 static void ppi_ipc_to_rtc(union rtc_sync_channels channels, bool setup) in ppi_ipc_to_rtc() argument
76 nrf_ipc_event_t ipc_evt = nrf_ipc_receive_event_get(channels.ch.ipc_in); in ppi_ipc_to_rtc()
77 uint32_t task_addr = z_nrf_rtc_timer_capture_task_address_get(channels.ch.rtc); in ppi_ipc_to_rtc()
80 nrfx_gppi_task_endpoint_setup(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
81 nrf_ipc_publish_set(NRF_IPC, ipc_evt, channels.ch.ppi); in ppi_ipc_to_rtc()
83 nrfx_gppi_task_endpoint_clear(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
90 * @param channels Details about channels
93 static void ppi_rtc_to_ipc(union rtc_sync_channels channels, bool setup) in ppi_rtc_to_ipc() argument
95 uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc); in ppi_rtc_to_ipc()
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | io-channels.h | 3 * @brief IO channels devicetree macro public API header file.
20 * @defgroup devicetree-io-channels Devicetree IO Channels API
28 * io-channels property at an index
37 * io-channels = <&adc1 10>, <&adc2 20>;
45 * @param node_id node identifier for a node with an io-channels property
46 * @param idx logical index into io-channels property
55 * io-channels property by name
64 * io-channels = <&adc1 10>, <&adc2 20>;
73 * @param node_id node identifier for a node with an io-channels property
74 * @param name lowercase-and-underscores name of an io-channels element
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| /Zephyr-latest/tests/subsys/lorawan/channels_mask/src/ |
| D | main.c | 14 * @brief Test channels mask with size 1
16 * This test will request the channels mask changes, passing valid
32 /* Configure channels mask with expected parameters */ in ZTEST()
34 zassert_equal(err, 0, "Denied right channels mask configuration"); in ZTEST()
36 /* Configure channels mask with unexpected channels mask size */ in ZTEST()
40 /* Configure channels mask with pointer to NULL */ in ZTEST()
46 * @brief Test channels mask with size 6
48 * This test will request the channels mask changes, passing valid
64 /* Configure channels mask with expected parameters */ in ZTEST()
66 zassert_equal(err, 0, "Denied right channels mask configuration"); in ZTEST()
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| /Zephyr-latest/dts/bindings/mbox/ |
| D | nxp,s32-mru.yaml | 15 to group hardware channel's mailboxes in logical channels.
20 of receive channels on the MRU instance coupled with the core, for instance in
23 channels on which the sender is intended to transmit.
25 For example, core B and C want to send messages to core A in channels 0 and 1,
30 rx-channels = <2>;
47 rx-channels:
51 Number of receive channels enabled on this instance.
52 Setting this value to N, will enable channels 0 to N-1, consecutively.
55 For example, if receiver A wants to Rx on channels 0 and 1, then A must
56 set rx-channels of mruA as follows:
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| D | nxp,mbox-imx-mu.yaml | 12 rx-channels:
16 Number of receive channels enabled on this instance.
17 Setting this value to N, will enable channels 0 to N-1, consecutively.
20 For example, if receiver A wants to Rx on channels 0 to 3, then A must
21 set rx-channels of muA as follows:
24 rx-channels = <4>;
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| D | nxp,mbox-mailbox.yaml | 20 rx-channels:
24 Number of receive channels enabled on this instance.
25 Setting this value to N, will enable channels 0 to N-1, consecutively.
28 For example, if receiver A wants to Rx on channels 0 to 3, then A must
29 set rx-channels of mailbox as follows:
32 rx-channels = <4>;
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| /Zephyr-latest/drivers/dma/ |
| D | dma_rpi_pico.c | 31 uint32_t channels; member
50 struct dma_rpi_pico_channel *channels; member
119 if (channel >= cfg->channels) { in dma_rpi_pico_config()
120 LOG_ERR("channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, channel); in dma_rpi_pico_config()
179 data->channels[channel].config = dma_channel_get_default_config(channel); in dma_rpi_pico_config()
181 data->channels[channel].source_address = (void *)dma_cfg->head_block->source_address; in dma_rpi_pico_config()
182 data->channels[channel].dest_address = (void *)dma_cfg->head_block->dest_address; in dma_rpi_pico_config()
183 data->channels[channel].block_size = dma_cfg->head_block->block_size; in dma_rpi_pico_config()
184 channel_config_set_read_increment(&data->channels[channel].config, in dma_rpi_pico_config()
187 channel_config_set_write_increment(&data->channels[channel].config, in dma_rpi_pico_config()
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| D | dma_wch.c | 30 struct dma_wch_chan_regs channels[DMA_WCH_MAX_CHAN]; member
49 struct dma_wch_channel *channels; member
73 return (regs->channels[ch].CFGR & DMA_CFGR1_EN) > 0 && in dma_wch_busy()
197 data->channels[ch].user_data = dma_cfg->user_data; in dma_wch_config()
198 data->channels[ch].dma_cb = dma_cfg->dma_callback; in dma_wch_config()
200 regs->channels[ch].CFGR = 0; in dma_wch_config()
208 regs->channels[ch].PADDR = paddr; in dma_wch_config()
209 regs->channels[ch].MADDR = maddr; in dma_wch_config()
210 regs->channels[ch].CNTR = cntr; in dma_wch_config()
211 regs->channels[ch].CFGR = cfgr; in dma_wch_config()
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| /Zephyr-latest/subsys/task_wdt/ |
| D | task_wdt.c | 40 /* array of all task watchdog channels */
41 static struct task_wdt_channel channels[CONFIG_TASK_WDT_CHANNELS]; variable
68 /* find minimum timeout of all channels */ in schedule_next_timeout()
69 for (int id = 0; id < ARRAY_SIZE(channels); id++) { in schedule_next_timeout()
70 if (channels[id].reload_period != 0 && in schedule_next_timeout()
71 channels[id].timeout_abs_ticks < next_timeout) { in schedule_next_timeout()
73 next_timeout = channels[id].timeout_abs_ticks; in schedule_next_timeout()
113 if (bg_channel || channels[channel_id].reload_period == 0) { in task_wdt_trigger()
118 if (channels[channel_id].callback) { in task_wdt_trigger()
119 channels[channel_id].callback(channel_id, in task_wdt_trigger()
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| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf54h20_cpurad.dtsi | 60 owned-channels = <7 8 9 10 11 12 13 14 15>;
61 child-owned-channels = <8 9 10 11 12>;
62 nonsecure-channels = <8 9 10 11 12>;
69 owned-channels = <0 2 3>;
70 sink-channels = <0 2>;
71 source-channels = <3>;
72 nonsecure-channels = <0 2 3>;
77 owned-channels = <0 2 3>;
78 sink-channels = <3>;
79 source-channels = <0 2>;
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| D | nrf9280_cpurad.dtsi | 53 owned-channels = <7 8 9 10 11 12 13 14 15>;
54 child-owned-channels = <8 9 10 11 12>;
55 nonsecure-channels = <8 9 10 11 12>;
62 owned-channels = <0>;
63 sink-channels = <0>;
64 nonsecure-channels = <0>;
69 owned-channels = <0>;
70 source-channels = <0>;
71 nonsecure-channels = <0>;
76 owned-channels = <0>;
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| /Zephyr-latest/dts/bindings/dma/ |
| D | espressif,esp32-gdma.yaml | 11 The GDMA controller in ESP32-C3 has six independent channels,
12 three transmit channels and three receive channels.
24 The GDMA controller in ESP32-S3 has ten independent channels,
25 five transmit channels and five receive channels. Only six are
26 supported, meaning three transmit and three receive channels.
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| D | st,stm32-dma.yaml | 8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
32 offset in the table of channels when mapping to a DMAMUX
34 for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
35 for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
36 plus the nb of dma channels of the 1st dma instance, etc.
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| /Zephyr-latest/tests/drivers/build_all/sensor/ |
| D | adc.dtsi | 16 io-channels = <&test_adc 0>;
22 io-channels = <&test_adc 1>;
32 io-channels = <&test_adc 2>;
60 io-channels = <&test_adc 0>;
70 io-channels = <&test_adc 0>;
79 io-channels = <&test_adc 0>;
88 io-channels = <&test_adc 0>;
97 io-channels = <&test_adc 0>;
103 io-channels = <&test_adc 0>;
112 io-channels = <&test_adc 0>;
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| /Zephyr-latest/dts/bindings/dac/ |
| D | adi,max22017-dac.yaml | 13 num-channels:
15 description: Number of DAC output channels.
33 Unipolar/bipolar mode selection for channels.
41 Voltage/current mode selection for channels.
49 Latch mode selection for channels.
52 mode. The latch mode can be used eitheir with the ldac-gpios to load both channels at the
60 Overcurrent mode selection for channels.
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| /Zephyr-latest/include/zephyr/drivers/sensor/ |
| D | vl53l0x.h | 8 * @brief Custom channels and values for VL53L0X ToF Sensor
10 * These channels provide additional sensor data not covered by the standard
11 * Zephyr sensor channels. Application must include vl53l0x.h file to gain
12 * access to these channels.
29 /* VL53L0x specific channels */
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| /Zephyr-latest/drivers/adc/ |
| D | adc_sam_afec.c | 52 * channels in the sequence: this buffer changes by that amount
53 * so all the channels would get repeated.
57 /* Bit mask of the channels to be sampled. */
58 uint32_t channels; member
113 /* Set single ended channels to unsigned and differential channels in adc_sam_channel_setup()
129 data->channel_id = find_lsb_set(data->channels) - 1; in adc_sam_start_conversion()
133 /* Disable all channels. */ in adc_sam_start_conversion()
151 * all channels as a group.
157 data->channels = ctx->sequence.channels; in adc_context_start_sampling()
193 uint32_t channels = sequence->channels; in start_read() local
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| D | adc_renesas_rz.c | 28 /** Mask for channels existed in each board */
52 /** Mask with channels that will be sampled */
53 uint32_t channels; member
59 * @brief Setup channels before starting to scan ADC
86 LOG_ERR("Differential channels are not supported"); in adc_rz_channel_setup()
100 /** Enable channels. */ in adc_rz_channel_setup()
119 uint32_t channels = 0; in adc_rz_isr() local
122 channels = data->channels; in adc_rz_isr()
123 for (channel_id = 0; channels > 0; channel_id++) { in adc_rz_isr()
124 /** Get channel ids from scan mask "channels" */ in adc_rz_isr()
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| D | adc_mcp320x.c | 29 uint8_t channels; member
37 uint8_t channels; member
69 if (channel_cfg->channel_id >= config->channels) { in mcp320x_channel_setup()
84 uint8_t channels = 0; in mcp320x_validate_buffer_size() local
88 for (mask = BIT(config->channels - 1); mask != 0; mask >>= 1) { in mcp320x_validate_buffer_size()
89 if (mask & sequence->channels) { in mcp320x_validate_buffer_size()
90 channels++; in mcp320x_validate_buffer_size()
94 needed = channels * sizeof(uint16_t); in mcp320x_validate_buffer_size()
118 if (find_msb_set(sequence->channels) > config->channels) { in mcp320x_start_read()
119 LOG_ERR("unsupported channels in mask: 0x%08x", in mcp320x_start_read()
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| /Zephyr-latest/samples/subsys/llext/edk/app/include/ |
| D | app_api.h | 18 enum Channels { enum
27 __syscall int publish(enum Channels channel, void *data,
29 __syscall int receive(enum Channels channel, void *data,
31 __syscall int register_subscriber(enum Channels channel,
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| /Zephyr-latest/drivers/firmware/scmi/ |
| D | Kconfig | 52 bool "Transport layer has static channels"
54 Enable this if the SCMI transport layer uses static channels.
55 What this means is that each protocol will have its channels
58 allocation scheme (i.e: use protocol-specific channels if
59 they exist, otherwise use base protocol channels).
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| /Zephyr-latest/drivers/sensor/ |
| D | default_rtio_sensor.c | 46 * @brief Compute the number of samples needed for the given channels
48 * @param[in] channels Array of channels requested
49 * @param[in] num_channels Number of channels on the @p channels array
50 * @return The number of samples required to read the given channels
52 static inline int compute_num_samples(const struct sensor_chan_spec *const channels, in compute_num_samples() argument
58 num_samples += SENSOR_CHANNEL_3_AXIS(channels[i].chan_type) ? 3 : 1; in compute_num_samples()
95 * @param[in] num_channels The number of valid channels in the header so far
104 if (sensor_chan_spec_eq(header->channels[i], chan_spec)) { in check_header_contains_channel()
120 const struct sensor_chan_spec *const channels = cfg->channels; in sensor_submit_fallback_sync() local
121 const int num_output_samples = compute_num_samples(channels, cfg->count); in sensor_submit_fallback_sync()
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| /Zephyr-latest/tests/bsim/bluetooth/host/l2cap/general/src/ |
| D | main_l2cap_ecred.c | 67 static struct channel channels[L2CAP_CHANNELS]; variable
84 k_work_queue_init(&channels[i].work_queue); in init_workqs()
85 k_work_queue_start(&channels[i].work_queue, stack_area[i], in init_workqs()
119 if (channels[SHORT_MSG_CHAN_IDX].sdus_received != in chan_recv_cb()
120 (channels[LONG_MSG_CHAN_IDX].sdus_received + 1)) { in chan_recv_cb()
220 struct channel *chan = &channels[idx]; in get_free_channel()
227 channels[idx].in_use = true; in get_free_channel()
265 for (int i = 0; i < ARRAY_SIZE(channels); i++) { in disconnect_all_channels()
266 if (channels[i].in_use) { in disconnect_all_channels()
267 LOG_DBG("Disconnecting channel: %d)", channels[i].chan_id); in disconnect_all_channels()
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