| /Zephyr-Core-3.5.0/samples/sensor/ccs811/ |
| D | README.rst | 48 BASELINE fff4
53 BASELINE fff4
61 BASELINE 8384
66 BASELINE 8384
71 BASELINE 8384
76 BASELINE 8384
81 BASELINE 8384
86 BASELINE 8384
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| D | Kconfig | 35 bool "Display BASELINE register value for each sample"
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/sensor/ |
| D | ccs811.h | 111 * @brief Fetch the current value of the BASELINE register.
113 * The BASELINE register encodes data used to correct sensor readings
116 * For proper management of the BASELINE register see AN000370
117 * "Baseline Save and Restore on CCS811".
127 * @brief Update the BASELINE register.
129 * For proper management of the BASELINE register see AN000370
130 * "Baseline Save and Restore on CCS811".
134 * @param baseline the value to be stored in the BASELINE register.
138 int ccs811_baseline_update(const struct device *dev, uint16_t baseline);
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| D | mhz19b.h | 25 /** Automatic Baseline Correction Self Calibration Function. */
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| /Zephyr-Core-3.5.0/subsys/net/ip/ |
| D | Kconfig.stack | 15 This value is a baseline and the actual TX stack size might
24 This value is a baseline and the actual RX stack size might
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| /Zephyr-Core-3.5.0/cmake/toolchain/llvm/ |
| D | target.cmake | 14 # ARMv8-M baseline is ARMv6-M with additional features from ARMv8-M.
22 # Baseline implementation processor is used.
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| /Zephyr-Core-3.5.0/arch/arm/core/cortex_m/ |
| D | Kconfig | 131 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline
148 In an ARMv8-M Baseline implementation with the Security Extension
179 supporting the Baseline implementation.
183 is also referred to as a Baseline Implementation. A
184 Baseline implementation has a subset of the instructions,
197 ARMv8-M Baseline includes additional features
251 implementation (Baseline or Mainline) supporting the
334 This is only required but not limited to Cortex-M Baseline CPUs
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| D | irq_relay.S | 11 * Armv8-M baseline SoCs
13 * In certain ARMv6-M and Armv8-M baseline cores the vector table address can
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| /Zephyr-Core-3.5.0/samples/sensor/ccs811/src/ |
| D | main.c | 42 int baseline = -1; in do_fetch() local
47 baseline = rc; in do_fetch()
66 printk("BASELINE %04x\n", baseline); in do_fetch()
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| /Zephyr-Core-3.5.0/dts/bindings/counter/ |
| D | espressif,esp32-rtc-timer.yaml | 10 supporting applications that need to keep a timing baseline on
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| /Zephyr-Core-3.5.0/drivers/sensor/ccs811/ |
| D | ccs811.c | 126 uint16_t baseline; in ccs811_baseline_fetch() local
130 rc = i2c_write_read_dt(&config->i2c, &cmd, sizeof(cmd), (uint8_t *)&baseline, in ccs811_baseline_fetch()
131 sizeof(baseline)); in ccs811_baseline_fetch()
134 rc = baseline; in ccs811_baseline_fetch()
141 uint16_t baseline) in ccs811_baseline_update() argument
144 uint8_t buf[1 + sizeof(baseline)]; in ccs811_baseline_update()
148 memcpy(buf + 1, &baseline, sizeof(baseline)); in ccs811_baseline_update()
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| /Zephyr-Core-3.5.0/doc/develop/test/ |
| D | ztest_deprecated.rst | 133 ztest_register_test_suite(baseline, pragma_always,
146 /* Should run `baseline` test suite only. */
151 /* Should run `baseline` and `before_usb` test suites. */
156 /* Should run `baseline` and `with_usb` test suites. */
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm/ |
| D | asm_inline_gcc.h | 37 * On ARMv6-M and ARMv8-M Baseline CPUs, this function reads the value of
66 /* armv8-m.baseline's mov is limited to registers r0-r7. in arch_irq_lock()
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| /Zephyr-Core-3.5.0/arch/arm/core/ |
| D | irq_offload.c | 26 /* ARMv6-M/ARMv8-M Baseline HardFault if you make a SVC call with in arch_irq_offload()
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| /Zephyr-Core-3.5.0/tests/arch/arm/arm_thread_swap/ |
| D | README.txt | 29 The test is currently supported in ARM Cortex-M Baseline and Mainline
42 The test is currently supported in ARM Cortex-M Baseline and Mainline
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| /Zephyr-Core-3.5.0/doc/develop/sca/ |
| D | codechecker.rst | 67 …ODECHECKER_EXPORT=<type>`` parameter. Allowed types are: ``html,json,codeclimate,gerrit,baseline``.
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm/cortex_m/ |
| D | exc.h | 24 * (e.g. Cortex-M Baseline variants), hardware ensures processor faults
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| /Zephyr-Core-3.5.0/include/zephyr/logging/ |
| D | log_multidomain_helper.h | 13 * This module aims to provide baseline for links and backends and simplify
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| /Zephyr-Core-3.5.0/scripts/pylib/twister/twisterlib/ |
| D | twister_main.py | 101 previous_results_file = os.path.join(options.outdir, "baseline.json")
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| /Zephyr-Core-3.5.0/modules/ |
| D | Kconfig.mcuboot | 28 (or Armv8-M baseline) targets with no built-in vector relocation
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| /Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s06/doc/ |
| D | index.rst | 193 …rm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc550x-s0x-baseline-arm-cortex-m33-ba…
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| /Zephyr-Core-3.5.0/tests/arch/arm/arm_thread_swap/src/ |
| D | arm_thread_arch.c | 467 /* For Cortex-M Baseline architecture, we verify that in ZTEST()
698 /* For Cortex-M Baseline architecture, we verify that in ZTEST()
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| /Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/src/ |
| D | arm_interrupt.c | 441 * In Cortex-M Baseline system calls cannot be invoked in ZTEST_USER()
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| /Zephyr-Core-3.5.0/doc/hardware/arch/ |
| D | arm_cortex_m.rst | 222 *Baseline* Cortex-M, this is actually enforced by hardware, as HardFault
241 In Baseline Cortex-M the priority level of SVC may be shared with other exceptions
270 In Baseline Cortex-M locking interrupts is implemented using the PRIMASK register.
588 Baseline Cortex-M platforms without VTOR register might not be able to relocate their
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| /Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s16/doc/ |
| D | index.rst | 226 …rm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc551x-s1x-baseline-arm-cortex-m33-ba…
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