Searched full:vectored (Results 1 – 25 of 116) sorted by relevance
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/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/common/ |
D | vector.S | 32 * CLIC vectored mode 34 * CLIC vectored mode uses mtvec exclusively for exception handling and 39 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */ 43 * CLIC vectored mode has a similar concept to CLINT vectored mode, 45 * However, in CLIC vectored mode, the handler table contains the 49 * When an interrupt occurs in CLIC vectored mode, the address of the 60 * CLINT vectored mode 64 * address of _irq_vector_table to indicate that vectored mode 72 addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
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/Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
D | Kconfig.vim | 9 bool "TI Vectored Interrupt Manager" 13 The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
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D | intc_nuclei_eclic.c | 70 /** 0: non-vectored 1:vectored */
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D | intc_dw.c | 11 * No support for vectored interrupts
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/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/ |
D | Kconfig | 32 bool "Should the SOC use vectored mode" 35 Should the SOC use vectored mode.
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/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/opentitan/ |
D | Kconfig.series | 8 # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
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/Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/ |
D | arm,v7m-nvic.yaml | 1 description: ARMv7-M NVIC (Nested Vectored Interrupt Controller)
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D | arm,v8m-nvic.yaml | 1 description: ARMv8-M NVIC (Nested Vectored Interrupt Controller)
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D | ti,vim.yaml | 7 TI Vectored Interrupt Manager is a external interrupt controller
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D | arm,v6m-nvic.yaml | 1 description: ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller
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D | arm,v8.1m-nvic.yaml | 1 description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)
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/Zephyr-Core-3.5.0/boards/arm/bbc_microbit/doc/ |
D | index.rst | 19 * :abbr:`NVIC (Nested Vectored Interrupt Controller)` 57 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/qemu_cortex_m0/doc/ |
D | index.rst | 14 * Nested Vectored Interrupt Controller 31 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/nrf52_vbluno52/doc/ |
D | index.rst | 14 * :abbr:`NVIC (Nested Vectored Interrupt Controller)` 43 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/qemu_cortex_m3/doc/ |
D | index.rst | 13 * Nested Vectored Interrupt Controller 31 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/arch/arm/ |
D | Kconfig | 35 the ARM Nested Vectored Interrupt Controller (NVIC).
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/Zephyr-Core-3.5.0/boards/arm/bcm958402m2_m7/doc/ |
D | index.rst | 27 | NVIC | on-chip | nested vectored interrupt controller |
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/Zephyr-Core-3.5.0/boards/arm/bcm958401m2/doc/ |
D | index.rst | 27 | NVIC | on-chip | nested vectored interrupt controller |
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/Zephyr-Core-3.5.0/boards/arm/arduino_due/doc/ |
D | index.rst | 13 * Nested Vectored Interrupt Controller (NVIC) 40 | NVIC | on-chip | nested vectored | 72 A Cortex-M3/4-based board uses vectored exceptions. This means each exception
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/Zephyr-Core-3.5.0/boards/arm/nrf52_adafruit_feather/doc/ |
D | index.rst | 13 * :abbr:`NVIC (Nested Vectored Interrupt Controller)` 53 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/arch/arm/core/ |
D | Kconfig.vfp | 16 This option signifies the support for a Vectored Floating-Point (VFP)
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/Zephyr-Core-3.5.0/boards/arm/bbc_microbit_v2/doc/ |
D | index.rst | 51 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/nuvoton_pfm_m487/doc/ |
D | index.rst | 46 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/nrf51_blenano/doc/ |
D | index.rst | 27 | NVIC | on-chip | nested vectored |
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/Zephyr-Core-3.5.0/boards/arm/numaker_pfm_m467/doc/ |
D | index.rst | 45 | NVIC | on-chip | nested vectored |
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