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/Zephyr-Core-3.5.0/dts/arm/microchip/mec172x/
Dmec172x-vw-routing.dtsi11 mchp-xec-espi-vw-routing {
12 compatible = "microchip,xec-espi-vw-routing";
14 /* eSPI Virtual Vire (VW) routing */
17 vw-reg = <0x02 MSVW 0 0>;
18 vw-girq = <24 0>;
22 vw-reg = <0x02 MSVW 0 1>;
23 vw-girq = <24 1>;
27 vw-reg = <0x02 MSVW 0 2>;
28 vw-girq = <24 2>;
32 vw-reg = <0x03 MSVW 1 0>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/
Dnpcx-espi-vws-map.dtsi12 * | VW idx | SLV reg | Wire Bit 3 | Wire Bit 2 | Wire Bit 1| Wire Bit 0 |
34 compatible = "nuvoton,npcx-espi-vw-conf";
36 /* eSPI Virtual Vire (VW) input configuration */
38 vw-slp-s3 {
39 vw-reg = <NPCX_VWEVMS0 0x01>;
40 vw-wui = <&wui_vw_slp_s3>;
42 vw-slp-s4 {
43 vw-reg = <NPCX_VWEVMS0 0x02>;
44 vw-wui = <&wui_vw_slp_s4>;
46 vw-slp-s5 {
[all …]
/Zephyr-Core-3.5.0/dts/bindings/espi/
Dnuvoton,npcx-espi-vw-conf.yaml4 description: Nuvoton NPCX eSPI Virtual Wire (VW) mapping child node
6 compatible: "nuvoton,npcx-espi-vw-conf"
10 Child node to to present the mapping between VW signal, its core register and input source of
14 vw-reg:
17 description: vw signal's register index and vw bitmask.
19 vw-wui:
22 Mapping table between Wake-Up Input (WUI) and vw input signal.
25 vw-wui = <&wui_vw_slp_s5>;
Dmicrochip,xec-espi-vw-routing.yaml6 compatible: "microchip,xec-espi-vw-routing"
13 VW registers and ECIA GIRQ registers.
15 vw-reg:
18 description: vw signal's register index and vw bitmask.
20 vw-girq:
26 to GIRQ24 b[5]. vw-girq = <24 5>;
45 affects all four virtual wires in the VW group.
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dsoc_dt.h42 * b[1] = VW direction 0(EC target to host controller), 1(host controller to EC target)
47 #define MCHP_DT_ESPI_VW_FLAGS(vw) \ argument
48 ((uint8_t)(MCHP_DT_VW_NODE_HAS_STATUS(vw)) & 0x01U) | \
49 ((((uint8_t)DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 1)) & 0x1) << 1) | \
50 ((((uint8_t)DT_ENUM_IDX_OR(MCHP_DT_NODE_FROM_VWTABLE(vw), reset_state, 0)) & 0x3) << 2) | \
51 ((((uint8_t)DT_ENUM_IDX_OR(MCHP_DT_NODE_FROM_VWTABLE(vw), reset_source, 0)) & 0x7) << 4)
53 /* Macro for the eSPI driver VW table entries.
55 * vw is a node from the XEC ESPI VW routing file.
57 #define MCHP_DT_ESPI_VW_ENTRY(e, vw) \ argument
59 .host_idx = DT_PROP_BY_IDX(MCHP_DT_NODE_FROM_VWTABLE(vw), vw_reg, 0), \
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-espi-vws-map.dtsi7 /* Common eSPI Virtual Wire (VW) mapping configurations in npcx family */
11 * Specific eSPI Virtual Wire (VW) mapping configurations in npcx4 series
13 * | VW idx | SLV reg | Wire Bit 3 | Wire Bit 2 | Wire Bit 1| Wire Bit 0 |
25 compatible = "nuvoton,npcx-espi-vw-conf";
32 vw-reg = <NPCX_VWGPSM0 0x01>;
35 vw-reg = <NPCX_VWGPSM0 0x02>;
38 vw-reg = <NPCX_VWGPSM0 0x04>;
41 vw-reg = <NPCX_VWGPSM0 0x08>;
46 vw-reg = <NPCX_VWGPSM1 0x01>;
49 vw-reg = <NPCX_VWGPSM1 0x02>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-espi-vws-map.dtsi7 /* Common eSPI Virtual Wire (VW) mapping configurations in npcx family */
11 * Specific eSPI Virtual Wire (VW) mapping configurations in npcx9 series
13 * | VW idx | SLV reg | Wire Bit 3 | Wire Bit 2 | Wire Bit 1| Wire Bit 0 |
25 compatible = "nuvoton,npcx-espi-vw-conf";
32 vw-reg = <NPCX_VWGPSM0 0x01>;
35 vw-reg = <NPCX_VWGPSM0 0x02>;
38 vw-reg = <NPCX_VWGPSM0 0x04>;
41 vw-reg = <NPCX_VWGPSM0 0x08>;
46 vw-reg = <NPCX_VWGPSM1 0x01>;
49 vw-reg = <NPCX_VWGPSM1 0x02>;
[all …]
/Zephyr-Core-3.5.0/subsys/emul/espi/
Demul_espi_host.c108 * @param vw Virtual wire signal to be found
113 enum espi_vwire_signal vw) in emul_host_find_index() argument
118 if (data->vw_state[idx].sig == vw) { in emul_host_find_index()
127 enum espi_vwire_signal vw, uint8_t level) in emul_host_set_vw() argument
132 idx = emul_host_find_index(data, vw); in emul_host_set_vw()
135 LOG_ERR("%s: invalid vw: %d", __func__, vw); in emul_host_set_vw()
145 enum espi_vwire_signal vw, uint8_t *level) in emul_host_get_vw() argument
150 idx = emul_host_find_index(data, vw); in emul_host_get_vw()
153 LOG_ERR("%s: invalid vw: %d", __func__, vw); in emul_host_get_vw()
162 int emul_espi_host_send_vw(const struct device *espi_dev, enum espi_vwire_signal vw, in emul_espi_host_send_vw() argument
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/espi/
Dnpcx_espi.h9 /* eSPI VW Master to Slave Register Index */
21 /* eSPI VW Slave to Master Register Index */
35 /* eSPI VW GPIO Slave to Master Register Index */
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-espi-vws-map.dtsi7 /* Common eSPI Virtual Wire (VW) mapping configurations in npcx family */
10 /* Specific eSPI Virtual Wire (VW) mapping configurations in npcx7 series */
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_espi_vw.h13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
143 /* Master-to-Slave VW byte indices(offsets) */
155 /* Slave-to-Master VW byte indices(offsets) */
296 /** @brief HW implements 11 Host-to-Target VW registers as an array */
301 /** @brief HW implements 11 Host-to-Target VW registers as named registers */
316 /** @brief eSPI M2S VW registers as an array of words at 0x400F9C00 */
336 /** @brief HW implements 11 Target-to-Host VW registers as an array */
341 /** @brief HW implements 11 Target-to-Host VW registers as named registers */
356 /** @brief eSPI S2M VW registers as an array of words at 0x400F9E00 */
Dmec172x_espi_iom.h85 /* Virtual Wire(VW) Capabilities */
153 /* VW Ready */
176 /* VW Error Status */
194 /* VW Channel Enable Status */
/Zephyr-Core-3.5.0/include/zephyr/drivers/
Despi_emul.h42 * @param vw The signal to be set.
48 typedef int (*emul_espi_api_set_vw)(const struct emul *target, enum espi_vwire_signal vw,
56 * @param vw The signal to be get.
62 typedef int (*emul_espi_api_get_vw)(const struct emul *target, enum espi_vwire_signal vw,
146 * @param vw The signal to be set.
152 int emul_espi_host_send_vw(const struct device *espi_dev, enum espi_vwire_signal vw, uint8_t level);
Despi.h436 enum espi_vwire_signal vw,
439 enum espi_vwire_signal vw,
904 * | | | VW CH ready| eSPI host
905 * | | IRQ +<------------+ enables VW
/Zephyr-Core-3.5.0/drivers/espi/
Despi_npcx.c109 uint8_t reg_idx; /* register index for VW signal */
110 uint8_t bitmask; /* VW signal bits-mask */
111 struct npcx_wui vw_wui; /* WUI mapping in MIWU modules for VW signal */
117 uint8_t reg_idx; /* register index for VW signal */
118 uint8_t bitmask; /* VW signal bits-mask */
122 * eSPI VW input/Output signal configuration tables. Please refer
185 /* eSPI VW service function forward declarations */
197 /* VW signal which has no wake-up input source */ in espi_init_wui_callback()
231 /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */ in espi_bus_reset_isr()
250 * If host enable/disable channel for VW/OOB/FLASH, EC should follow in espi_bus_cfg_update_isr()
[all …]
Despi_emul.c133 static int espi_emul_send_vwire(const struct device *dev, enum espi_vwire_signal vw, uint8_t level) in espi_emul_send_vwire() argument
153 return api->set_vw(emul->target, vw, level); in espi_emul_send_vwire()
156 static int espi_emul_receive_vwire(const struct device *dev, enum espi_vwire_signal vw, in espi_emul_receive_vwire() argument
177 return api->get_vw(emul->target, vw, level); in espi_emul_receive_vwire()
Despi_mchp_xec_v2.c78 * VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
100 * These are configurable by overriding device tree vw routing |
309 return -EIO; /* VW not enabled */ in espi_xec_send_vwire()
354 return -EIO; /* VW not enabled */ in espi_xec_receive_vwire()
896 /* VW channel interrupt can disabled at this point */ in espi_vw_chan_en_isr()
1086 * VW handlers must have signature
1292 .vw_base_addr = DT_INST_REG_ADDR_BY_NAME(0, vw),
1364 * Reset VW values SRC[3:0] located in b[15:12].
1365 * MSVW current VW state values located in bits[64, 72, 80, 88]
1366 * SMVW current VW state values located in bits[32, 40, 48, 56]
[all …]
Despi_mchp_xec.c117 * VW Idx | VW reg | SRC_ID3 | SRC_ID2 | SRC_ID1 | SRC_ID0 |
830 * of VW wires as 1111b in bits [15:12]. in espi_config_vw_ocb()
841 /* Set INDEX field with OCB VW index */ in espi_config_vw_ocb()
994 /* VW channel interrupt can disabled at this point */ in espi_vwire_chanel_isr()
1198 /* Configure spare VW register SMVW06 to VW index 50h. As per in vw_sus_warn_isr()
1199 * per microchip recommendation, spare VW register should be in vw_sus_warn_isr()
1200 * configured between SLAVE_BOOT_LOAD_DONE = 1 VW event and in vw_sus_warn_isr()
1201 * point where SUS_ACK=1 VW is sent to SOC. in vw_sus_warn_isr()
1492 /* Max VW count is 12 pairs */ in espi_xec_init()
DKconfig69 early in the flow after the VW channel is configured. Or it could be
Despi_it8xxx2.c112 uint8_t vw_index; /* VW index of signal */
579 /* VW signals used in eSPI */
1368 LOG_INF("VW PLTRST_L %sasserted", pltrst ? "de" : ""); in espi_vw_pltrst_isr()
1467 LOG_INF("vw isr %s is ignored!", __func__); in espi_it8xxx2_vwidx43_isr()
1478 LOG_INF("vw isr %s is ignored!", __func__); in espi_it8xxx2_vwidx44_isr()
1497 * The ISR of espi VW interrupt in array needs to match bit order in
1498 * ESPI VW VWCTRL1 register.
1512 * This is used to record the previous VW valid/level field state to discover
1577 * VW channel enable asserted flag.
1889 /* Enable espi vw interrupt */ in espi_it8xxx2_init()
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dsoc_dt.h278 * @brief Get phandle from vw-wui property of child node with that path.
281 * @return phandle from "vw-wui" prop of child node with that path.
287 * @brief Construct a npcx_wui structure from vw-wui property of a child node
302 * @brief Construct a npcx espi device configuration of vw input signal from
305 * @signal vw input signal name.
320 * @brief Construct a npcx espi device configuration of vw output signal from
323 * @signal vw output signal name.
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec1727nsz.dtsi15 #include "mec172x/mec172x-vw-routing.dtsi"
/Zephyr-Core-3.5.0/samples/drivers/espi/
Dsample.yaml31 - "espi: VW channel is ready"
DREADME.rst44 VW channel is ready
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dchip_chipregs.h2014 * eSPI VW registers
2017 /* 0x00-0x7f: VW index */
2021 /* 0x90: VW Contrl 0 */
2023 /* 0x91: VW Contrl 1 */
2025 /* 0x92: VW Contrl 2 */
2027 /* 0x93: VW Contrl 3 */
2031 /* 0x95: VW Contrl 5 */
2033 /* 0x96: VW Contrl 6 */
2035 /* 0x97: VW Contrl 7 */

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