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/Zephyr-Core-3.5.0/scripts/west_commands/runners/
Ddediprog.py4 # SPDX-License-Identifier: Apache-2.0
14 DEFAULT_MAX_RETRIES = 3
17 '''Runner front-end for DediProg (dpcmd).'''
19 def __init__(self, cfg, spi_image, vcc, retries): argument
22 self.vcc = vcc
35 parser.add_argument('--spi-image', required=True,
37 parser.add_argument('--vcc',
38 help='VCC (0=3.5V, 1=2.5V, 2=1.8V)')
39 parser.add_argument('--retries', default=5,
46 vcc=args.vcc,
[all …]
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-mkr-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
23 16 A1/D16 VCC -
24 17 A2/D17 GND -
25 18 A3/D18 RESET -
[all …]
Dsparkfun-pro-micro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
10 Proceeding counter-clockwise:
11 * A 12-pin Power and Digital Input header. This has input signals
13 * An 12-pin Power and Digital/Analog Input header. This
15 non-monotonically decreasing numbering.
19 0 TX0 RAW -
20 1 RX1 GND -
21 - GND RST -
22 - GND VCC -
24 3 D3 D20/A2 20
[all …]
/Zephyr-Core-3.5.0/tests/boards/mec172xevb_assy6906/i2c_api/
DREADME.txt17 * JP49 1-2 Connected Connect PCA9555 VCC to +3.3V_STBY
18 * JP53 1-2 Connected Select address 0100b, which means 0x26
19 * JP12 13-14 Connected Connect I2C01_SDA from CPU to header J20
20 * JP12 4-5 Connected Connect I2C01_SCL from CPU to header J20
22 * JP77 7-8 Connected External pull-up for I2C01_SDA
23 * JP77 9-10 Connected External pull-up for I2C01_SCL
26 * JP58.3 J20.3 Connected Connect NXP PCA95xx to I2C01
/Zephyr-Core-3.5.0/samples/sensor/tmp116/
DREADME.rst29 * Breakout **GND** pin <--> Nucleo **GND** pin
30 * Breakout **VCC** pin <--> Nucleo **3V3** pin
31 * Breakout **SDA** pin <--> Nucleo **CN5-D14** pin
32 * Breakout **SCL** pin <--> Nucleo **CN5-D15** pin
40 .. zephyr-app-commands::
41 :zephyr-app: samples/sensor/tmp116
58 .. code-block:: console
60 Device TMP116 - 0x200010a8 is ready
/Zephyr-Core-3.5.0/samples/sensor/ti_hdc/
DREADME.rst33 * Breakout **GND** pin <--> Nucleo **GND** pin
34 * Breakout **VCC** pin <--> Nucleo **3V3** pin
35 * Breakout **SDA** pin <--> Nucleo **CN7-D14** pin
36 * Breakout **SCL** pin <--> Nucleo **CN7-D15** pin
44 .. zephyr-app-commands::
45 :zephyr-app: samples/sensor/ti_hdc/
52 .. code-block:: console
65 .. code-block:: bash
67 …HYR_BASE/scripts/twister -T $ZEPHYR_BASE/samples/sensor/ti_hdc/ -p nucleo_l496zg --device-testing …
72 .. code-block:: bash
[all …]
/Zephyr-Core-3.5.0/boards/arm/acn52832/doc/
Dindex.rst10 nRF52832 ARM Cortex-M4F CPU and the following devices:
16 * :abbr:`I2C (Inter-Integrated Circuit)`
23 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
32 Additionally to the SoC the board provides an on-board antenna with a RF matching circuit,
33 two external oscillators with 32 MHz and 32.768 kHz, load capacitors, a tag-connector
34 and a RGB-LED.
40 ------
42 +-------+-------------+--------------------+---------------+
43 | PIN # | Tag-Connect | NRF52832 Functions | Configuration |
46 +-------+-------------+--------------------+---------------+
[all …]
/Zephyr-Core-3.5.0/boards/xtensa/heltec_wifi_lora32_v2/
Dheltec_wifi_lora32_v2.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "heltec_wifi_lora32_v2-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 uart-0 = &uart0;
18 i2c-0 = &i2c0;
26 compatible = "gpio-leds";
34 label = "External VCC";
44 compatible = "gpio-keys";
55 zephyr,shell-uart = &uart0;
[all …]
/Zephyr-Core-3.5.0/boards/arm/lora_e5_dev_board/doc/
Dlora_e5_dev_board.rst3 Seeed Studio LoRa-E5 Dev Board
9 The LoRa-E5 Dev Board is a compact board for the evaluation of the
10 Seeed Studio LoRa-E5 STM32WLE5JC module.
11 The LoRa-E5-HF STM32WLE5JC Module supports multiple LPWAN protocols on the
13 All GPIOs of the LoRa-E5 Module are laid out supporting
14 various data protocols and interfaces including RS-485 and Grove.
18 :alt: LoRa-E5 Dev board
23 The boards LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
24 and a 32.768kHz crystal oscillator in a 28-pin SMD package.
25 This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
[all …]
/Zephyr-Core-3.5.0/boards/arm/96b_aerocore2/doc/
Dindex.rst10 STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones.
26 - STM32F427VIT6 in LQFP100 package
27 - ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
28 - 168 MHz max CPU frequency
29 - VDD from 1.7 V to 3.6 V
30 - 2048 KB Flash
31 - 256 KB SRAM
32 - GPIO with external interrupt capability
33 - 12-bit ADC with 16 channels
34 - RTC
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec172xevb_assy6906/doc/
Dindex.rst21 - MEC172x ARM Cortex-M4 Processor
22 - 416 KB RAM and 128 KB boot ROM
23 - Keyboard interface
24 - ADC & GPIO headers
25 - UART0 and UART1
26 - FAN0, FAN1, FAN2 headers
27 - FAN PWM interface
28 - JTAG/SWD, ETM and MCHP Trace ports
29 - PECI interface 3.0
30 - I2C voltage translator
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec15xxevb_assy6853/doc/
Dindex.rst13 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
25 - MEC1521HA0SZ ARM Cortex-M4 Processor
26 - 256 KB RAM and 64 KB boot ROM
27 - Keyboard interface
28 - ADC & GPIO headers
29 - UART0, UART1, and UART2
30 - FAN0, FAN1, FAN2 headers
31 - FAN PWM interface
32 - JTAG/SWD, ETM and MCHP Trace ports
33 - PECI interface 3.0
[all …]
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dchip_chipregs.h3 * SPDX-License-Identifier: Apache-2.0
44 /* --- General Control (GCTRL) --- */
201 volatile uint8_t Reserved4[3];
226 /* 0x049: PWM Output Open-Drain Enable */
235 #define IT8XXX2_PWM_T0DVS BIT(3)
241 /* --- Wake-Up Control (WUC) --- */
244 /* TODO: should a defined interface for configuring wake-up interrupts */
348 #define IT8XXX2_WDT_LEWDCNTL BIT(3)
359 #define IT8XXX2_WDT_ET2TC BIT(3)
365 /* External Timer 3~8 control */
[all …]
/Zephyr-Core-3.5.0/boards/shields/atmel_rf2xx/doc/
Dindex.rst11 true SPI-to-antenna solution and can be operated by any external
20 There are compatible designations for `AT AVR-RZ600`_ and `AT REB233-XPRO`_.
21 This means, any Atmel board with 10-pin Xplained or 20-pin Xplained Pro
33 The RZ600 Development Kit needs Atmel Xplained or Xplained-Pro header
36 selected. For Xplained-Pro header the `atmel_rf2xx_legacy`_ must be enabled.
40 :alt: AVR-RZ600
45 +---------+--------+-------------------------------------+
48 | 1 | RST | GPIO - Reset |
49 +---------+--------+-------------------------------------+
50 | 2 | MISC | DNU - Do Not Use |
[all …]
/Zephyr-Core-3.5.0/boards/arm/olimexino_stm32/doc/
Dindex.rst3 OLIMEXINO-STM32
9 The OLIMEXINO-STM32 board is based on the STMicroelectronics STM32F103RB ARM
10 Cortex-M3 CPU.
14 :alt: OLIMEXINO-STM32
16 OLIMEXINO-STM32
19 `OLIMEXINO-STM32 website`_ and `OLIMEXINO-STM32 user manual`_.
29 +-----------+------------+-------------------------+
32 | NVIC | on-chip | nested vectored |
34 +-----------+------------+-------------------------+
35 | SYSTICK | on-chip | system clock |
[all …]
/Zephyr-Core-3.5.0/include/zephyr/sd/
Dsd_spec.h4 * SPDX-License-Identifier: Apache-2.0
31 SD_SEND_RELATIVE_ADDR = 3,
32 MMC_SEND_RELATIVE_ADDR = 3,
66 * to inform the SD card the next command is an application-specific one.
84 /* Bits 0-2 reserved */
85 SD_R1_AUTH_ERR = BIT(3),
96 /* Bits 17-18 reserved */
139 SDMMC_R1_STANDBY = 3U,
156 SD_SPI_R1CMD_CRC_ERR = BIT(3),
181 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1)
[all …]
/Zephyr-Core-3.5.0/doc/hardware/peripherals/
D1-Wire_bus_topology.drawio.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- Do not edit this file with editors other than diagrams.net -->
3 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
4 …-0.5 -0.5 521 171" content="&lt;mxfile host=&quot;Electron&quot; modified=&quot;2022-07-04T19:35:4…
/Zephyr-Core-3.5.0/boards/arm/stm32_min_dev/doc/
Dindex.rst10 breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There
13 - Blue Pill Board
14 - Black Pill Board
59 +--------+---------------+
63 +--------+---------------+
65 +--------+---------------+
67 +--------+---------------+
68 | V3 | VCC |
69 +--------+---------------+
76 silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) : in wuesr()
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5)); in wuesr()
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
[all …]
/Zephyr-Core-3.5.0/boards/arm/bt510/doc/
Dbt510.rst9 …tooth v5 Long Range integrated sensor that uses a Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU.
17 * :abbr:`I2C (Inter-Integrated Circuit)`
24 * :abbr:`UART (Universal Asynchronous Receiver-Transmitter)`
51 +-----------+------------+----------------------+
54 | ADC | on-chip | adc |
55 +-----------+------------+----------------------+
56 | CLOCK | on-chip | clock_control |
57 +-----------+------------+----------------------+
58 | FLASH | on-chip | flash |
59 +-----------+------------+----------------------+
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec172xmodular_assy6930/doc/
Dmec172xmodular_assy6930.rst22 - MEC172x (MEC1723, MEC1727 and MEC1728) ARM Cortex-M4 Processor
23 - 416 KB RAM and 128 KB boot ROM
24 - UART1 using microUSB
25 - PECI interface 3.0
26 - FAN, PWM and TACHO pins
27 - 5 SMBus instances
28 - eSPI header
29 - VCI interface
30 - 1 hardware driven PS/2 ports
31 - Keyboard interface headers
[all …]
/Zephyr-Core-3.5.0/boards/arm/96b_carbon/doc/
Dindex.rst9 The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and
13 STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to
14 the Cortex-M4 CPU over SPI for Bluetooth LE connectivity. Even though
18 - The ``96b_carbon`` configuration is used when developing programs for
24 - The ``96b_carbon_nrf51`` configuration should be used for programming
49 - STM32F401RET6 in LQFP64 package
50 - ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
51 - 84 MHz max CPU frequency
52 - VDD from 1.7 V to 3.6 V
53 - 512 KB Flash
[all …]
/Zephyr-Core-3.5.0/boards/xtensa/yd_esp32/doc/
Dindex.rst3 YD-ESP32
9 The YD-ESP32 development board is one of VCC-GND® Studio’s official boards.
10 This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core.
14 :alt: YD-ESP32
16 YD-ESP32 DevKit with ESP32-WROOM-32E Module
22 with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a
23 Tensilica Xtensa LX6 microprocessor in both dual-core and single-core
25 Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm
30 - Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz
31 - 520KB of SRAM
[all …]
/Zephyr-Core-3.5.0/boards/arm/96b_nitrogen/doc/
Dindex.rst10 nRF52832 ARM Cortex-M4F CPU.
27 - nRF52832 microcontroller with 512kB Flash, 64kB RAM
28 - ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
29 - Bluetooth LE
30 - NFC
31 - LPC11U35 on board SWD debugger
33 - SWD debugger firmware
34 - USB to UART
35 - Drag and Drop firmware upgrade
37 - 7 LEDs
[all …]
/Zephyr-Core-3.5.0/boards/arm/olimex_stm32_e407/doc/
Dindex.rst3 OLIMEX-STM32-E407
9 The OLIMEX-STM32-E407 board is open source hardware and is based on
10 the STMicroelectronics STM32F407ZG ARM Cortex-M4 CPU.
14 :alt: OLIMEX-STM32-E407
16 OLIMEX-STM32-E407
22 `OLIMEX-STM32-E407 website`_ and `OLIMEX-STM32-E407 user manual`_.
32 +------------+------------+----------------------+
35 | NVIC | on-chip | nested vectored |
37 +------------+------------+----------------------+
38 | SYSTICK | on-chip | system clock |
[all …]

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