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/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_xilinx_axi.h22 REG_TX_FIFO = 0x108, /* Transmit FIFO */
25 REG_TX_FIFO_OCY = 0x114, /* Transmit FIFO Occupancy */
48 ISR_TX_HALF_EMPTY = BIT(7), /* Transmit FIFO Half Empty */
53 ISR_TX_FIFO_EMPTY = BIT(2), /* Transmit FIFO Empty */
54 ISR_TX_ERR_TARGET_COMP = BIT(1), /* Transmit Error/Target Transmit Complete */
67 CR_TXAK = BIT(4), /* Transmit Acknowledge Enable */
68 CR_TX = BIT(3), /* Transmit/Receive Mode Select */
70 CR_TX_FIFO_RST = BIT(1), /* Transmit FIFO Reset */
76 SR_TX_FIFO_EMPTY = BIT(7), /* Transmit FIFO empty */
79 SR_TX_FIFO_FULL = BIT(4), /* Transmit FIFO full */
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s69/
Dpinmux.c24 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_pinmux_init()
29 /* Select Data in from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_pinmux_init()
31 /* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */ in lpcxpresso_55s69_pinmux_init()
39 /* Set Transmit I2S - Flexcomm 7 SCK, WS from shared signal set 0 */ in lpcxpresso_55s69_pinmux_init()
46 /* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */ in lpcxpresso_55s69_pinmux_init()
/Zephyr-Core-3.5.0/boards/arm/mimxrt685_evk/
Dinit.c18 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ in mimxrt685_evk_init()
23 /* Select Data in from Transmit I2S - Flexcomm 3 */ in mimxrt685_evk_init()
25 /* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ in mimxrt685_evk_init()
33 /* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ in mimxrt685_evk_init()
40 /* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ in mimxrt685_evk_init()
/Zephyr-Core-3.5.0/samples/net/wpanusb/
Dwpan-radio-spec.txt25 Opcode 0x01 - Transmit bRequest
30 Transmit data from Host to Device
32 Opcode 0x02 - Transmit Async bRequest
98 Transmit ACK
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_sam_gmac_priv.h133 * Transmit buffer descriptor bit field definitions
136 /** Transmit buffer length */
142 /** Transmit IP/TCP/UDP checksum generation offload errors */
144 /** Late collision, transmit error detected */
146 /** Transmit frame corruption due to AHB error */
148 /** Retry limit exceeded, transmit error detected */
150 /** Last descriptor in Transmit Descriptor list */
152 /** Buffer used, must be 0 for the GMAC to read data to the transmit buffer */
218 /** Receive/transmit buffer descriptor */
224 /** Ring list of receive/transmit buffer descriptors */
[all …]
Deth_w5500_priv.h33 #define W5500_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
34 #define W5500_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
35 #define W5500_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
Deth_e1000_priv.h19 #define ICR_TXDW (1) /* Transmit Descriptor Written Back */
20 #define ICR_TXQE (1 << 1) /* Transmit Queue Empty */
41 TCTL = 0x0400, /* Transmit Control */
/Zephyr-Core-3.5.0/modules/canopennode/
DKconfig36 int "Stack size for the CANopen transmit workqueue"
39 Size of the stack used for the internal CANopen transmit
43 int "Priority for CANopen transmit workqueue"
47 Priority level of the internal CANopen transmit workqueue.
/Zephyr-Core-3.5.0/dts/bindings/dma/
Despressif,esp32-gdma.yaml12 three transmit channels and three receive channels.
25 five transmit channels and five receive channels. Only six are
26 supported, meaning three transmit and three receive channels.
/Zephyr-Core-3.5.0/drivers/serial/
Duart_pl011_registers.h53 #define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
55 #define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
99 #define PL011_CR_TXE BIT(8) /* transmit enable */
101 #define PL011_CR_DTR BIT(10) /* data transmit ready */
130 #define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
149 #define PL011_RIS_TXRIS BIT(5) /* Transmit interrupt status */
Duart_rcar.c45 #define SCFTDR 0x0c /* Transmit FIFO Data Register */
65 #define SCSCR_TEIE BIT(11) /* Transmit End Interrupt Enable */
66 #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
68 #define SCSCR_TE BIT(5) /* Transmit Enable */
78 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger 1 */
79 #define SCFCR_TTRG0 BIT(4) /* Transmit FIFO Data Count Trigger 0 */
81 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
96 #define SCFSR_TDFE BIT(5) /* Transmit FIFO Data Empty */
167 /* Wait for empty space in transmit FIFO */ in uart_rcar_poll_out()
197 /* Disable Transmit and Receive */ in uart_rcar_configure()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/mbox/
Dnxp,s32-mru.yaml22 receiver to be able to transmit on it. There is no need to define the transmit
23 channels on which the sender is intended to transmit.
/Zephyr-Core-3.5.0/dts/bindings/ethernet/
Dsilabs,gecko-ethernet.yaml63 description: Transmit data 0 individual pin configuration defined as <location port pin>
68 description: Transmit data 1 individual pin configuration defined as <location port pin>
73 description: Transmit enable individual pin configuration defined as <location port pin>
/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_dw1000_regs.h134 /* Transmit Frame Control */
138 /* Bit mask to access Transmit Frame Length */
140 /* Bit mask to access Transmit Frame Length Extension */
144 /* Bit mask to access Transmit Bit Rate */
146 /* Bit mask to access Transmit Pulse Repetition Frequency */
148 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
152 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
156 /* Transmit Bit Rate = 110k */
158 /* Transmit Bit Rate = 850k */
160 /* Transmit Bit Rate = 6.8M */
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/
Dboard.c116 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */ in mimxrt595_evk_init()
121 /* Select Data in from Transmit I2S - Flexcomm 3 */ in mimxrt595_evk_init()
123 /* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */ in mimxrt595_evk_init()
131 /* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */ in mimxrt595_evk_init()
138 /* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */ in mimxrt595_evk_init()
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Dcc13xx_cc26xx-pinctrl.h17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
23 #define IOC_PORT_MCU_UART0_TX 0x00000010 /* MCU UART0 Transmit Pin */
27 #define IOC_PORT_MCU_UART1_TX 0x00000014 /* MCU UART1 Transmit Pin */
40 #define IOC_PORT_MCU_SSI1_TX 0x00000022 /* MCU SSI1 Transmit Pin */
/Zephyr-Core-3.5.0/include/zephyr/mgmt/mcumgr/transport/
Dserial.h41 * @param data The data to transmit.
42 * @param len The number of bytes to transmit.
76 * @param cb A callback used to transmit raw bytes.
/Zephyr-Core-3.5.0/doc/connectivity/usb/device/api/
Dusb_device.rst9 There are two ways to transmit data, using the 'low' level read/write API or
13 To transmit data to the host, the class driver should call usb_write().
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/mesh/src/
Dtest_persistence.c74 .transmit = BT_MESH_TRANSMIT(2, 20), \
84 .transmit = BT_MESH_TRANSMIT(2, 20), \
94 .transmit = BT_MESH_TRANSMIT(3, 20), \
104 .transmit = BT_MESH_TRANSMIT(3, 20), \
114 .transmit = 0, \
205 uint8_t transmit; member
222 .relay = { .state = BT_MESH_FEATURE_ENABLED, .transmit = BT_MESH_TRANSMIT(2, 20) },
238 .relay = { .state = BT_MESH_FEATURE_ENABLED, .transmit = BT_MESH_TRANSMIT(1, 10) },
338 ASSERT_EQUAL(expected->transmit, got->transmit); in check_mod_pub_params()
886 uint8_t transmit; in test_cfg_save() local
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/Zephyr-Core-3.5.0/doc/connectivity/networking/
Dnet_pkt_processing_stats.rst15 options that control this. For transmit (TX) path the option is called
37 transmit or receive queues defined in the system. These are controlled by
60 * Packet is about to be placed to transmit queue. The time it took from network
62 * The correct TX thread is invoked, and the packet is read from the transmit
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Dsoc_espi_saf_v2.h109 * Transmit one byte opcode at 1X (no DMA).
178 /* Continuous mode read: transmit-quad 24-bit address and mode byte */
185 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
218 /* Enter Continuous mode: transmit-single CM quad read opcode */
225 /* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
240 /* Enter Continuous mode: transmit-single CM dual read opcode */
247 /* Enter Continuous mode: transmit-dual 24-bit address and mode byte */
305 /* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
325 /* Enter Continuous mode: transmit-single CM quad read opcode */
332 /* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
[all …]
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/
Dintel_adsp_ipc.h148 * @param data 30 bits value to transmit with the message (IDR register).
149 * @param ext_data Extended value to transmit with the message (IDD register).
162 * @param data 30 bits value to transmit with the message (IDR register)
163 * @param ext_data Extended value to transmit with the message (IDD register)
177 * @param data 30 bits value to transmit with the message (IDR register).
178 * @param ext_data Extended value to transmit with the message (IDD register).
/Zephyr-Core-3.5.0/include/zephyr/console/
Dtty.h69 * @brief Set transmit timeout for tty device.
96 * @brief Set transmit buffer for tty device.
98 * Set transmit buffer or switch to unbuffered operation for transmit.
/Zephyr-Core-3.5.0/subsys/net/lib/sntp/
Dsntp_pkt.h42 uint32_t tx_tm_s; /* Transmit timestamp seconds */
43 uint32_t tx_tm_f; /* Transmit timestamp seconds fraction */
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Dsoc_espi_saf_v1.h85 * Transmit one byte opcode at 1X (no DMA).
153 /* Continuous mode read: transmit-quad 24-bit address and mode byte */
160 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */
175 /* Enter Continuous mode: transmit-single CM quad read opcode */
182 /* Enter Continuous mode: transmit-quad 24-bit address and mode byte */
226 /* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */
246 /* Enter Continuous mode: transmit-single CM quad read opcode */
253 /* Enter Continuous mode: transmit-quad 32-bit address and mode byte */
316 * QMSPI descriptors describing SPI opcode transmit and

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