| /Zephyr-Core-3.5.0/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_copro.h | 22 * @brief FT8xx co-processor engine functions
23 * @defgroup ft8xx_copro FT8xx co-processor
28 /** Co-processor widget is drawn in 3D effect */
30 /** Co-processor option to decode the JPEG image to RGB565 format */
32 /** Co-processor option to decode the JPEG image to L8 format, i.e., monochrome */
36 /** Co-processor widget is drawn without 3D effect */
40 /** Co-processor widget centers horizontally */
42 /** Co-processor widget centers vertically */
44 /** Co-processor widget centers horizontally and vertically */
48 /** Co-processor widget has no background drawn */
[all …]
|
| /Zephyr-Core-3.5.0/samples/net/openthread/coprocessor/ |
| D | README.rst | 2 :name: OpenThread co-processor
5 Build a Thread border-router using OpenThread's co-processor designs.
10 OpenThread Co-Processor allows building a Thread Border Router. The code in this
12 The Co-Processor can act in two variants: Network Co-Processor (NCP) and Radio
13 Co-Processor (RCP), see https://openthread.io/platforms/co-processor.
19 The preferred Co-Processor configuration of OpenThread is RCP now.
|
| /Zephyr-Core-3.5.0/boards/riscv/niosv_g/doc/ |
| D | index.rst | 13 Nios® V/g Processor Intel® FPGA IP
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 …t/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/g processor system.
|
| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | Kconfig.xlnx_ps | 2 # Xilinx Processor System MIO / EMIO GPIO controller driver
10 bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
15 Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
|
| /Zephyr-Core-3.5.0/boards/x86/intel_adl/doc/ |
| D | index.rst | 8 Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer
11 Currently supported is N-processor line, Single Chip Platform that consists of
12 the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on
15 Proposed branding for Adler Lake N is Intel Processor (N100,N200) and
64 .. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core…
|
| /Zephyr-Core-3.5.0/boards/riscv/niosv_m/doc/ |
| D | index.rst | 13 Nios® V/m Processor Intel® FPGA IP
23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
55 Use the JTAG UART terminal to print the stdout and stderr of the Nios® V/m processor system.
|
| /Zephyr-Core-3.5.0/dts/bindings/iio/adc/ |
| D | nxp,vf610-adc.yaml | 38 processor can access to this peripheral. User can select to assign this
39 peripheral to the M4 processor, A9 processor or both with R/W or RW
44 RDC_DOMAIN_PERM_RW. Example to allow both processor to read/write to
|
| /Zephyr-Core-3.5.0/doc/hardware/peripherals/ |
| D | peci.rst | 11 The PECI interface allows external devices to read processor temperature,
12 perform processor manageability functions, and manage processor interface
|
| /Zephyr-Core-3.5.0/arch/sparc/core/ |
| D | sw_trap_set_pil.S | 14 * Set processor interrupt level
23 * - %i0: New processor interrupt level
26 * - %i0: Old processor interrupt level
|
| /Zephyr-Core-3.5.0/boards/arm/rcar_h3_salvatorx/support/ |
| D | openocd.cfg | 39 # This function make use of A5x processor to:
42 # - Halt the processor
63 # resume a5x processor or cmt timer will not run
65 # set CR7 processor as default target for future commands
72 # Resume the A57 processor and gives
|
| /Zephyr-Core-3.5.0/boards/arm/rcar_h3ulcb/support/ |
| D | openocd.cfg | 39 # This function make use of A5x processor to:
42 # - Halt the processor
63 # resume a5x processor or cmt timer will not run
65 # set CR7 processor as default target for future commands
72 # Resume the A57 processor and gives
|
| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | Kconfig.xlnx | 5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
|
| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/niosv/ |
| D | Kconfig.soc | 9 bool "Intel FPGA NIOSV Microcontroller Core Processor"
18 bool "Intel FPGA NIOSV General Purpose Processor"
|
| /Zephyr-Core-3.5.0/subsys/net/l2/openthread/ |
| D | Kconfig | 218 bool "OpenThread Co-Processor"
223 Enable Co-Processor in OpenThread stack.
228 prompt "OpenThread Co-Processor type"
230 This option selects Thread network co-processor type
233 bool "NCP - Network Co-Processor"
235 bool "RCP - Radio Co-Processor"
239 int "Set Co-Processor UART ring buffer size"
242 TX buffer size for the OpenThread Co-Processor UART.
|
| /Zephyr-Core-3.5.0/drivers/ipm/ |
| D | Kconfig | 4 bool "Inter-Processor Mailbox (IPM) drivers"
6 Include interrupt-based inter-processor mailboxes
55 Inter Processor Interrupt driver for AMD-Xilinx
|
| D | Kconfig.stm32 | 13 int "STM32 IPCC Processor ID"
18 use to define the Processor ID for IPCC access
|
| /Zephyr-Core-3.5.0/drivers/crypto/ |
| D | Kconfig.mcux_dcp | 5 bool "NXP Data Co-Processor (DCP) driver"
12 Enable NXP Data Co-Processor (DCP) driver.
|
| /Zephyr-Core-3.5.0/arch/arm/core/cortex_m/ |
| D | Kconfig | 177 This option signifies the use of an ARMv6-M processor
178 implementation, or the use of an ARMv8-M processor
194 This option signifies the use of an ARMv8-M processor
209 This option signifies the use of an ARMv7-M processor
211 ARMv8-M processor implementation supporting the Main
229 This option signifies the use of an ARMv8-M processor
239 This option signifies the use of an ARMv8.1-M processor
250 This option signifies the use of an ARMv8-M processor
259 This option signifies the use of an ARMv7-M processor
260 implementation, or the use of an ARMv8-M processor
[all …]
|
| /Zephyr-Core-3.5.0/tests/subsys/mgmt/mcumgr/smp_version/ |
| D | testcase.yaml | 11 # FIXME: Exclude systems whereby the processor type is not known and emits a warning
24 # FIXME: Exclude systems whereby the processor type is not known and emits a warning
|
| /Zephyr-Core-3.5.0/modules/thrift/src/thrift/server/ |
| D | TServer.h | 92 * Called when a client is about to call the processor.
177 TServer(const std::shared_ptr<TProcessor> &processor) in TServer() argument
178 : processorFactory_(new TSingletonProcessorFactory(processor)) in TServer()
204 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
206 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
230 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
234 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
255 TServer(const std::shared_ptr<TProcessor> &processor, in TServer() argument
261 : processorFactory_(new TSingletonProcessorFactory(processor)), in TServer()
273 * call). This allows the TProcessorFactory to return a different processor
|
| /Zephyr-Core-3.5.0/boards/arm/mec172xmodular_assy6930/ |
| D | Kconfig.defconfig | 27 # processor clock divider register. We assume PCR processor clock divider
|
| /Zephyr-Core-3.5.0/boards/arm/mec172xevb_assy6906/ |
| D | Kconfig.defconfig | 27 # processor clock divider register. We assume PCR processor clock divider
|
| /Zephyr-Core-3.5.0/lib/open-amp/ |
| D | resource_table.h | 26 #define VRING_RX_ADDRESS -1 /* allocated by Master processor */
27 #define VRING_TX_ADDRESS -1 /* allocated by Master processor */
28 #define VRING_BUFF_ADDRESS -1 /* allocated by Master processor */
|
| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/neorv32/ |
| D | Kconfig.series | 5 bool "NEORV32 Processor"
14 Enable support for the NEORV32 Processor (SoC).
|
| /Zephyr-Core-3.5.0/boards/riscv/neorv32/doc/ |
| D | index.rst | 9 The NEORV32 is an open-source RISC-V compatible processor system intended as a
10 ready-to-go auxiliary processor within larger SoC designs or as a stand-alone
15 - `The NEORV32 RISC-V Processor GitHub`_
16 - `The NEORV32 RISC-V Processor Datasheet`_
17 - `The NEORV32 RISC-V Processor User Guide`_
29 Processor (SoC):
46 The default board configuration for the NEORV32 Processor (SoC) can be found in
203 .. _The NEORV32 RISC-V Processor GitHub:
206 .. _The NEORV32 RISC-V Processor Datasheet:
209 .. _The NEORV32 RISC-V Processor User Guide:
|
