| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | nuvoton,npcx-pinctrl.yaml | 18 - psl-in-pol: Select the assertion detection polarity of PSL input
73 psl-polarity:
76 A map to DEVALTn that configures detection polarity of PSL input pads.
96 The assertion detection polarity of PSL input selection
97 - "low-falling": Select the detection polarity to low/falling
98 - "high-rising": Select the detection polarity to high/rising
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pwm/ |
| D | pwm.h | 39 * @name PWM polarity flags
41 * or pwm_configure_capture() to specify the polarity of a PWM channel.
46 /** PWM pin normal polarity (active-high pulse). */
49 /** PWM pin inverted polarity (active-low pulse). */
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| /Zephyr-Core-3.5.0/dts/bindings/display/panel/ |
| D | panel-timing.yaml | 86 Polarity of horizontal sync pulse
97 Polarity of vertical sync pulse
108 Polarity of data enable, sent with each horizontal interval.
119 Polarity of pixel clock. Selects which edge to drive data to display on.
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | lm77.yaml | 21 When present, the polarity on the INT signal is inverted (active-high).
26 When present, the polarity on the T_CRIT_A signal is inverted
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| D | bosch,bmm150.yaml | 13 The polarity default is active high when sensor data is ready.
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| /Zephyr-Core-3.5.0/dts/bindings/sdhc/ |
| D | zephyr,sdhc-spi-slot.yaml | 19 Clock polarity to use for SPI SDHC. Some cards respond properly
26 on the clock's polarity. When mode-cpol is set and this option as well,
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| /Zephyr-Core-3.5.0/dts/bindings/display/ |
| D | ftdi,ft800.yaml | 27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
28 the rising edge. If it is set to one, PCLK polarity is on
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| D | st,stm32-ltdc.yaml | 15 Configure the GPIO polarity (active high/active low) according to LCD datasheet.
21 Configure the GPIO polarity (active high/active low) according to LCD datasheet.
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 23 polarity = "ACTIVE_HIGH";
32 polarity = "ACTIVE_LOW";
41 polarity = "ACTIVE_LOW";
127 polarity:
130 Output polarity for PWM channel.
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| D | nordic,nrf-sw-pwm.yaml | 53 the polarity of its output is determined by the flag specified
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| /Zephyr-Core-3.5.0/boards/arm/mr_canhubk3/ |
| D | mr_canhubk3.dts | 448 polarity = "ACTIVE_HIGH";
457 polarity = "ACTIVE_HIGH";
466 polarity = "ACTIVE_HIGH";
475 polarity = "ACTIVE_HIGH";
484 polarity = "ACTIVE_HIGH";
493 polarity = "ACTIVE_HIGH";
502 polarity = "ACTIVE_HIGH";
511 polarity = "ACTIVE_HIGH";
519 polarity = "ACTIVE_LOW";
558 polarity = "ACTIVE_LOW";
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/ |
| D | pinctrl_soc.h | 59 * @brief Suppoerted PSL input detection polarity in NPCX series
77 /** The polarity for peripheral device functionality. */
106 * such as detection polarity, port number, and so on.
111 /** Related register group for detection polarity of PSL input. */
113 /** Related register bit for detection polarity of PSL input. */
234 * @param prop Property name for pull-up/down configuration. (i.e. 'polarity')
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/gpio/ |
| D | gpio_cmsdk_ahb.h | 38 /* Offset: 0x030 (r/w) interrupt polarity set register */
40 /* Offset: 0x034 (r/w) interrupt polarity clear register */
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| /Zephyr-Core-3.5.0/samples/sensor/qdec/boards/ |
| D | nucleo_f401re.overlay | 22 st,input-polarity-inverted;
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/ |
| D | mec_vci.h | 59 /* VCI Polarity register */
104 volatile uint32_t POLARITY; member
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | nxp,kinetis-lpuart.yaml | 30 description: RTS polarity at RS485 mode.
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| /Zephyr-Core-3.5.0/dts/bindings/power-domain/ |
| D | power-domain-gpio.yaml | 18 provide the GPIO polarity and open-drain status in the phandle
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_b91.c | 71 uint8_t polarity; /* Polarity: interrupt polarity: rising, falling */ member
182 /* Set polarity and level */ in gpio_b91_irq_set()
185 BM_CLR(gpio->polarity, BIT(pin)); in gpio_b91_irq_set()
190 BM_SET(gpio->polarity, BIT(pin)); in gpio_b91_irq_set()
195 BM_CLR(gpio->polarity, BIT(pin)); in gpio_b91_irq_set()
200 BM_SET(gpio->polarity, BIT(pin)); in gpio_b91_irq_set()
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| /Zephyr-Core-3.5.0/tests/drivers/pwm/pwm_loopback/boards/ |
| D | mr_canhubk3.overlay | 35 /delete-property/ polarity;
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| /Zephyr-Core-3.5.0/drivers/counter/ |
| D | counter_mcux_lptmr.c | 21 lptmr_pin_polarity_t polarity; member
135 lptmr_config.pinPolarity = config->polarity; in mcux_lptmr_init()
224 .polarity = DT_INST_PROP(0, active_low),
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| /Zephyr-Core-3.5.0/dts/bindings/regulator/ |
| D | regulator-fixed.yaml | 29 provide the GPIO polarity and open-drain status in the phandle
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/sensor/ |
| D | tmp108.h | 29 /** Set the alert pin polarity */
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| /Zephyr-Core-3.5.0/dts/bindings/led_strip/ |
| D | worldsemi,ws2812-spi.yaml | 29 description: Set SPI clock polarity.
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/memory-controller/ |
| D | stm32-fmc-nor-psram.h | 28 /* Wait Signal Polarity */
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_rpi_pico.c | 75 /* The pico_sdk only allows setting the polarity of both channels at once.
76 * This is a convenience function to make setting the polarity of a single
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