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/Zephyr-latest/dts/bindings/gpio/
Dparticle-gen3-header.yaml2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
Darduino-header-r3.yaml3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
[all …]
Datmel-xplained-pro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
10 to the embedded debugger. A header with ID7 signal from the embedded
15 header must always be implemented.
17 below the PWR header. This header must always be present.
19 This header is mandatory for medium and large boards and should not be
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
[all …]
Datmel-xplained-header.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
10 Xplained Pro standard connector keep compatibility with this header and it
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
36 Bind Pin Name Pin Pin Pin Name Bind
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
Darduino-mkr-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
23 16 A1/D16 VCC -
[all …]
Dadafruit-feather-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
24 1 A1 - EN
[all …]
Dpanasonic,reduced-arduino-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Panasonic's reduced Arduino header.
9 AREF -
10 GND -
11 - N/C D13 19
12 - IOREF D12 18
13 - RESET D11 17
14 - 3V3 D10 16
15 - 5V D9 NC
16 - GND D8 NC
[all …]
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 TI BoosterPack GPIO header
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
Dsparkfun,micromod-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
[all …]
Darduino-nano-header-r3.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
10 and GND (pin 4) pins are not exposed by this binding.
11 * A 15-pin Analog Input and power supply header. This has analog input
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
31 10 D10 AREF -
32 11 D11 3V3 -
[all …]
Dseeed-xiao-header.yaml4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
31 compatible: "seeed,xiao-gpio"
33 include: [gpio-nexus.yaml, base.yaml]
Dsparkfun-pro-micro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
10 Proceeding counter-clockwise:
11 * A 12-pin Power and Digital Input header. This has input signals
13 * An 12-pin Power and Digital/Analog Input header. This
15 non-monotonically decreasing numbering.
19 1 D1/TXO RAW -
20 0 D0/RXI GND -
21 - GND RST -
22 - GND VCC -
35 compatible: "sparkfun,pro-micro-gpio"
[all …]
Dm5stack,atom-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Pin-header exposed on M5Stack Atom devices.
15 compatible: "m5stack,atom-header"
17 include: [gpio-nexus.yaml, base.yaml]
Draspberrypi-40pins-header.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on Raspberry Pi 40-pin header.
7 The Raspberry Pi layout provides a 2x20 pins header.
11 - 3V3 5V -
12 0 GPIO2/I2C1_SDA 5V -
13 1 GPIO3/I2C1_SCL GND -
15 - GND GPIO15/UART0_RXD 4
17 7 GPIO27 GND -
19 - 3V3 GPIO24 10
20 11 GPIO10/SPI0_MOSI GND -
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/
Dquick_feather.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 out-gpios = <&gpio 2 0>; /* Header J8 - pin 6 */
11 in-gpios = <&gpio 0 0>; /* Header J8 - pin 10 */
/Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/
DREADME.rst1 .. zephyr:code-sample:: lsmd6dso_i2c_on_i3c
3 :relevant-api: sensor_interface
19 the evaluation board STEVAL-MKI196V1 connected to the I3C header
25 - LSM6DSO https://www.st.com/en/mems-and-sensors/lsm6dso.html
31 sensor (for example, the one on evaluation board STEVAL-MKI196V1).
36 .. zephyr-app-commands::
37 :zephyr-app: samples/sensor/lsm6dso_i2c_on_i3c
38 :host-os: unix
47 ------------------
50 header, where:
[all …]
/Zephyr-latest/boards/nxp/twr_ke18f/
DKconfig1 # TWR-KE18F board configuration
4 # SPDX-License-Identifier: Apache-2.0
9 bool "CLKOUT signal on FlexIO header"
12 Enable the CLKOUT signal on FlexIO header pin 7 (PTE10).
/Zephyr-latest/samples/sensor/lps22hh_i3c/
DREADME.rst1 .. zephyr:code-sample:: lps22hh_i3c
3 :relevant-api: sensor_interface
18 STEVALMKI192-V1 connected to the I3C header on :zephyr:board:`mimxrt685_evk`.
23 - LPS22HH: https://www.st.com/en/mems-and-sensors/lps22hh.html
29 sensor (for example, the one on evaluation board STEVALMKI192-V1).
34 I3C In-Band Interrupt (IBI) to signal new data being available.
45 .. zephyr-app-commands::
46 :zephyr-app: samples/sensor/lps22hh_i3c
47 :host-os: unix
56 ------------------
[all …]
/Zephyr-latest/scripts/utils/
Dpinctrl_nrf_migrate.py4 # SPDX-License-Identifier: Apache-2.0
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
31 [--header ""]
35 .. code-block:: devicetree
41 tx-pin = <5>;
[all …]
/Zephyr-latest/boards/silabs/radio_boards/
Dindex.rst22 - Wireless Starter Kit Mainboard (board BRD4001A, available standalone as SLWMB4001A)
23 - Wireless Pro Kit Mainboard (board BRD4002A, available standalone as Si-MB4002A)
26 the two boards are pin compatible for all shared functionality.
40 - Advanced Energy Monitor providing real-time information about energy consumption at up to 10 ksps
41 - Packet Trace Interface
42 - Virtual COM port
43 - On-board Segger J-Link debugger with USB and Ethernet interfaces
44 - Ultra-low power 128x128 pixel memory LCD
45 - 2 user buttons and 2 LEDs
46 - 20 pin 2.54mm expansion header
[all …]
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Dnucleo_f429zi.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 /* I2C bus pins are exposed on the ST morpho header.
6 * Pin Hdr Pin Hdr
10 * Short Pin PB9 to PB11, and PB8 to PB10, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 compatible = "zephyr,i2c-target-eeprom";
Dnucleo_l073rz.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 /* I2C bus pins are exposed on the ST morpho header.
6 * Pin Hdr Pin Hdr
10 * Short Pin PB9 to PB11, and PB8 to PB10, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
24 compatible = "zephyr,i2c-target-eeprom";
Dnucleo_f207zg.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 /* I2C bus pins are exposed on the ST morpho header.
6 * Pin Hdr Pin Hdr
10 * Short Pin PB9 to PB11, and PB8 to PB10, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 compatible = "zephyr,i2c-target-eeprom";
Dnucleo_f401re.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 /* I2C bus pins are exposed on the ST morpho header.
6 * Pin Hdr Pin Hdr
10 * Short Pin PB9 to PC9, and PB8 to PA8, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 compatible = "zephyr,i2c-target-eeprom";
Dnucleo_f091rc.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
3 /* I2C bus pins are exposed on the ST morpho header.
6 * Pin Hdr Pin Hdr
10 * Short Pin PB9 to PA12, and PB8 to PA11, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 /* i2c2 is disabled by default because of pin conflict with can1 */
26 compatible = "zephyr,i2c-target-eeprom";

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