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/Zephyr-latest/scripts/ci/coverage/
Dcoverage_analysis.py96 test_suite['status'] = 'mixed'
102 test_suite['status'] = 'mixed'
138 test_suite['status'] = 'mixed'
144 test_suite['status'] = 'mixed'
175 test_suite['status'] = 'mixed'
181 test_suite['status'] = 'mixed'
191 test_suite['status'] = 'mixed'
197 test_suite['status'] = 'mixed'
356 worksheet.write(row,col+6,"Mixed",header_format)
365 … testsuites,runnable,build_only,sim_only,hw_only, mixed= self._component_calculate_stats(item)
[all …]
/Zephyr-latest/samples/subsys/logging/syst/
DREADME.rst101 …[ 0.020000] <dbg> syst: mixed str dynamic str --- dynamic str --- another dynamic str --- anoth…
102 [ 0.020000] <dbg> syst: mixed c/s ! static str dynamic str static str !
162 mixed str dynamic str --- dynamic str --- another dynamic str --- another dynamic str
163 mixed c/s ! static str dynamic str static str !
185 mixed str dynamic str --- dynamic str --- another dynamic str --- another dynamic str
186 mixed c/s ! static str dynamic str static str !
272 …[ 0.020000] <dbg> syst: mixed str dynamic str --- dynamic str --- another dynamic str --- anoth…
273 [ 0.020000] <dbg> syst: mixed c/s ! static str dynamic str static str !
335 mixed str dynamic str --- dynamic str --- another dynamic str --- another dynamic str
336 mixed c/s ! static str dynamic str static str !
[all …]
/Zephyr-latest/dts/bindings/fpga/
Drenesas,slg47115.yaml4 description: Renesas SLG47115 GreenPAK Configurable Mixed-Signal IC
Drenesas,slg47105.yaml4 description: Renesas SLG47105 GreenPAK Configurable Mixed-Signal IC
Drenesas,slg471x5.yaml4 description: Renesas SLG47105/SLG47115 GreenPAK Configurable Mixed-Signal IC
/Zephyr-latest/drivers/fpga/
DKconfig.slg471x55 bool "Renesas SLG47105/SLG47115 GreenPAK Configurable Mixed-Signal IC"
/Zephyr-latest/samples/subsys/logging/dictionary/src/
Dmain.c56 LOG_DBG("mixed str %s %s %s %s %s %s %s", vs0, "---", vs0, "---", vs1, "---", vs1); in main()
57 LOG_DBG("mixed c/s %c %s %s %s %c", c, s, vs0, s, c); in main()
/Zephyr-latest/samples/subsys/logging/dictionary/
DREADME.rst77 …[ 217283] <dbg> hello_world: main: mixed str dynamic str --- dynamic str --- another dynamic st…
78 [ 266022] <dbg> hello_world: main: mixed c/s ! static str dynamic str static str !
/Zephyr-latest/tests/subsys/logging/dictionary/pytest/
Dtest_logging_dictionary.py100 # [ 10] <dbg> hello_world: main: mixed str dynamic str --- dynamic str \
102 re.compile(r'[\s]+[\[][0-9,:\. ]+[\]] <dbg> hello_world: main: mixed str dynamic str '
104 # [ 10] <dbg> hello_world: main: mixed c/s ! static str dynamic str static str !
105 re.compile(r'[\s]+[\[][0-9,:\. ]+[\]] <dbg> hello_world: main: mixed c/s ! static str '
/Zephyr-latest/tests/subsys/logging/dictionary/src/
Dmain.c57 LOG_DBG("mixed str %s %s %s %s %s %s %s", vs0, "---", vs0, "---", vs1, "---", vs1); in main()
58 LOG_DBG("mixed c/s %c %s %s %s %c", c, s, vs0, s, c); in main()
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-hsfll-local.yaml7 The local HSFLL mixed-mode IP generates several clock frequencies in the range
Dlitex,clkout.yaml7 LiteX Mixed Mode Clock Manager clock output binding
Dlitex,clk.yaml7 LiteX Mixed Mode Clock Manager
/Zephyr-latest/samples/subsys/logging/syst/src/
Dmain.c67 LOG_DBG("mixed str %s %s %s %s %s %s %s", vs0, "---", vs0, "---", vs1, "---", vs1); in log_msgs()
68 LOG_DBG("mixed c/s %c %s %s %s %c", c, s, vs0, s, c); in log_msgs()
/Zephyr-latest/scripts/checkpatch/
Dtimestamp19 # Some switches can be mixed and matched, eg. -Sa gives 2015-01-14-18-13
/Zephyr-latest/scripts/ci/
Dpylintrc79 mixed-line-endings,
158 mixed-format-string,
/Zephyr-latest/scripts/tracing/
Dtrace_capture_usb.py85 #try to read to avoid garbage mixed to useful stream data
/Zephyr-latest/include/zephyr/
Dsyscall.h34 * - Mixed or indeterminate code, these inlines will do a runtime check
/Zephyr-latest/doc/develop/languages/cpp/
Dindex.rst186 be mixed, etc.
205 style. In any case, both styles must never be mixed in the same
/Zephyr-latest/cmake/ide/
Declipse_cdt4_generator_amendment.cmake18 # generator projects that use mixed C/C++.
25 # In mixed C/C++ projects, the header files often contain the following
/Zephyr-latest/samples/drivers/clock_control_litex/
DREADME.rst11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
/Zephyr-latest/drivers/input/
Dinput_adc_keys.c105 * the mixed voltage that these keys are simultaneously pressed. in adc_keys_process()
/Zephyr-latest/tests/bluetooth/host/id/bt_setup_random_id_addr/src/
Dmain.c132 * Response length is properly configured, and response data contains a mixed data with
/Zephyr-latest/cmake/bintools/
Dbintools_template.cmake87 # disassembly_flag_inline_source : Flag to use to display source code mixed with disassembly
/Zephyr-latest/boards/st/nucleo_f303k8/doc/
Dindex.rst7 mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz.

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