| /Zephyr-Core-3.5.0/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 8 as a reference timebase (master bus) for other channels.
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
44 the master bus, the devicetree node should be enabled and dts properties
67 Channel identifier for the master bus.
73 A channel mask for channels that by hardware design can use this master bus
74 as timebase for the operation, lsb is channel 0. The mask bit for this master bus
75 must always 0 because a master bus should not do other thing than a base timer.
89 Master bus type.
102 Master bus mode.
111 Default period (in ticks) for master bus at boot time. This determines PWM period
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| /Zephyr-Core-3.5.0/subsys/net/l2/ethernet/gptp/ |
| D | gptp_data_set.h | 106 * This is used when determining the Grand Master.
176 /** Last Grand Master Frequency Change. */
182 /** Last Grand Master Frequency Change. */
188 /** Last Grand Master Phase Change. */
191 /** Last Grand Master Phase Change. */
203 /** Grand Master priority vector. */
206 /** Previous Grand Master priority vector. */
218 /** Grand Master Time Base Indicator. */
227 /** Steps removed from selected master. */
251 /** A Grand Master is present in the domain. */
[all …]
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| /Zephyr-Core-3.5.0/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 49 serial port, one is master another is remote:
56 RPMsg Service [master] demo started
57 Master core received a message: 1
58 Master core received a message: 3
59 Master core received a message: 5
61 Master core received a message: 99
100 and network core images, the following messages (one for master and one for
108 RPMsg Service [master] demo started
109 Master core received a message: 1
110 Master core received a message: 3
[all …]
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| D | sample.yaml | 17 - "Master core received a message: 1"
18 - "Master core received a message: 99"
|
| /Zephyr-Core-3.5.0/doc/contribute/coding_guidelines/ |
| D | index.rst | 68 …- `Dir 1.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_01_01.c>`_
75 …- `Dir 2.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_02_01.c>`_
82 …- `Dir 3.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_03_01.c>`_
89 …- `Dir 4.1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_01.c>`_
96 …- `Dir 4.2 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_02.c>`_
103 …- `Dir 4.4 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_04.c>`_
110 …- `Dir 4.5 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_05.c>`_
117 …- `Dir 4.6 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_06.c>`_
124 …- `Dir 4.7 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_07.c>`_
131 …example 1 <https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/D_04_08_1.c>`_
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 8 require to use a reference timebase from a master bus.
28 master-bus = <&emios1_bus_a>;
37 master-bus = <&emios1_bus_b>;
52 OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
53 phandle 'master-bus'. For OPWMB mode, PWM's period is master bus's period and
54 is 2 * master bus's period - 2 for OPWMCB mode. Please notice that the devicetree
55 node for master bus should be enabled and configured for using, please see
88 master-bus:
91 A phandle to master-bus node that will be used as external timebase
93 for PWM operation. A master bus must be used exclusively, such as if
[all …]
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| /Zephyr-Core-3.5.0/soc/x86/apollo_lake/doc/ |
| D | supported_features.txt | 19 configuration. The UARTs are fed a master clock which is fed into a PLL which
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
30 The resulting baud master clock frequency is ``(n/m)`` * master.
32 Typically, the master clock is 100MHz, and the firmware by default sets
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
36 Zephyr what the resulting master clock is.
56 and ``clock-frequency`` (the resulting baud master clock). The meaning of
|
| /Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc54xxx/gcc/ |
| D | startup_LPC54114_cm4.S | 34 * Determine if the core executing this code is the master or
58 mov r4, r5 /* Set flag for master core (1) */
60 /* Determine if M4 core is the master or slave */
66 ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
68 /* Select boot based on selected master core and core ID */
71 eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
93 /* Slave isn't yet setup for system boot from the master */
94 /* so sleep until the master sets it up and then reboots it */
98 wfi /* Sleep forever until master reboots */
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| /Zephyr-Core-3.5.0/drivers/w1/ |
| D | Kconfig.ds2485 | 1 # Configuration options for the Zephyr DS2485 1-Wire master driver
7 bool "DS2485 1-wire master driver"
13 Enable the ds2485 w1 master driver.
|
| /Zephyr-Core-3.5.0/lib/open-amp/ |
| D | resource_table.h | 20 #define VRING0_ID 0 /* (master to remote) fixed to 0 for Linux compatibility */
21 #define VRING1_ID 1 /* (remote to master) fixed to 1 for Linux compatibility */
26 #define VRING_RX_ADDRESS -1 /* allocated by Master processor */
27 #define VRING_TX_ADDRESS -1 /* allocated by Master processor */
28 #define VRING_BUFF_ADDRESS -1 /* allocated by Master processor */
|
| /Zephyr-Core-3.5.0/include/zephyr/net/ |
| D | dsa.h | 45 * master.
51 * - 0 if ok (packet sent via master iface), < 0 if error
84 * @param iface Network interface (master)
92 * @brief Pointer to master interface send function
97 * @brief DSA helper function to register transmit function for master
99 * @param iface Network interface (master)
100 * @param fn Pointer to master interface send method
108 * @brief DSA helper function to check if port is master
110 * @param iface Network interface (master)
129 /** Pointer to DSA master network interface */
[all …]
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_rcar.c | 39 #define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
41 #define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
43 #define RCAR_I2C_ICMSR 0x0c /* Master Status */
46 #define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
51 #define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
55 #define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
62 #define RCAR_I2C_MNR BIT(6) /* Master Nack Received */
63 #define RCAR_I2C_MAL BIT(5) /* Master Arbitration lost */
64 #define RCAR_I2C_MST BIT(4) /* Master Stop Transmitted */
65 #define RCAR_I2C_MDE BIT(3) /* Master Data Empty */
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/w1/ |
| D | zephyr,w1-serial.yaml | 4 # Properties for the serial 1-Wire master driver:
11 description: 1-Wire master over Zephyr uart
15 include: [uart-device.yaml, w1-master.yaml]
|
| D | maxim,ds2485.yaml | 4 # Properties for the DS2485 I2C 1-Wire master with memory driver:
7 This is a representation of the Maxim DS2485 I2C 1-Wire master w/ memory
|
| D | maxim,ds2482-800-channel.yaml | 4 description: DS4282-800, 8-Channel 1-Wire Master (Channel driver)
8 include: [w1-master.yaml]
|
| D | maxim,ds2484.yaml | 4 description: DS4284 Single-Channel 1-Wire Master
8 include: [i2c-device.yaml, w1-master.yaml]
|
| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | nordic,nrf-spi-common.yaml | 43 Optional bi-directional line that allows SPI master to indicate to SPI
50 master keeps the line in the low state
51 - when a transfer is to be performed, SPI master configures its WAKE
58 to SPI master that it can proceed with the transfer
60 and SPI master again keeps the line in the low state
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| /Zephyr-Core-3.5.0/dts/bindings/test/ |
| D | vnd,w1.yaml | 4 description: Test W1 bus master node
8 include: [w1-master.yaml]
|
| /Zephyr-Core-3.5.0/samples/subsys/ipc/openamp/ |
| D | README.rst | 69 serial port, one is master another is remote:
76 OpenAMP[master] demo started
77 Master core received a message: 1
78 Master core received a message: 3
79 Master core received a message: 5
81 Master core received a message: 99
|
| D | sample.yaml | 19 - "Master core received a message: 1"
20 - "Master core received a message: 99"
|
| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/espi/ |
| D | npcx_espi.h | 9 /* eSPI VW Master to Slave Register Index */
21 /* eSPI VW Slave to Master Register Index */
35 /* eSPI VW GPIO Slave to Master Register Index */
|
| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | Kconfig.esp32 | 7 bool "ESP32 SPI Master driver"
11 Enables support for ESP32 SPI Master driver.
|
| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | st,stm32-bxcan.yaml | 23 master-can-reg:
25 description: master can reg when different from current instance
|
| /Zephyr-Core-3.5.0/soc/arm/atmel_sam/same70/ |
| D | soc.c | 56 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
155 /* Switch MCK (Master Clock) to the main clock first */ in clock_init()
190 * Final setup of the Master Clock in clock_init()
203 /* Wait for Master Clock setup to complete */ in clock_init()
208 /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ in clock_init()
212 /* Wait for Master Clock setup to complete */ in clock_init()
217 /* Finally select PLL as Master Clock source */ in clock_init()
221 /* Wait for Master Clock setup to complete */ in clock_init()
241 * Set FWS (Flash Wait State) value before increasing Master Clock in z_arm_platform_init()
|
| /Zephyr-Core-3.5.0/soc/arm/atmel_sam/samv71/ |
| D | soc.c | 56 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
155 /* Switch MCK (Master Clock) to the main clock first */ in clock_init()
190 * Final setup of the Master Clock in clock_init()
203 /* Wait for Master Clock setup to complete */ in clock_init()
208 /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ in clock_init()
212 /* Wait for Master Clock setup to complete */ in clock_init()
217 /* Finally select PLL as Master Clock source */ in clock_init()
221 /* Wait for Master Clock setup to complete */ in clock_init()
241 * Set FWS (Flash Wait State) value before increasing Master Clock in z_arm_platform_init()
|
