Searched full:mcr0 (Results 1 – 5 of 5) sorted by relevance
17 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()39 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()41 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flash_init()42 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flash_init()
24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()35 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()37 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flash_init()38 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flash_init()
125 FLEXSPI2->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flexspi_enter_critical()136 FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flexspi_enter_critical()149 FLEXSPI2->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flexspi_exit_critical()150 FLEXSPI2->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flexspi_exit_critical()151 while (FLEXSPI2->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flexspi_exit_critical()160 FLEXSPI->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flexspi_exit_critical()161 FLEXSPI->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flexspi_exit_critical()162 while (FLEXSPI->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flexspi_exit_critical()
44 setting register field MCR0[COMBINATIONEN].61 Source clock for flash read. See the RXCLKSRC field in register MCR0.
359 data->base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in memc_flexspi_init()
