Searched full:j12 (Results 1 – 13 of 13) sorted by relevance
| /Zephyr-latest/boards/shields/p3t1755dp_ard_i2c/doc/ |
| D | index.rst | 33 J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090
39 J10, J11, J12 3-5, the i2c addr is 0x48
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| /Zephyr-latest/boards/shields/p3t1755dp_ard_i3c/doc/ |
| D | index.rst | 33 J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090
39 J10, J11, J12 3-5, the i2c addr is 0x48
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| /Zephyr-latest/tests/drivers/regulator/voltage/boards/ |
| D | lpcxpresso55s36.overlay | 9 /* To do this test, connect AN (J7-1) to VREF_OUT (J12-16) */
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | ambiq-header.yaml | 11 J7 J12
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| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/doc/ |
| D | index.rst | 46 17. PSOC 6 debug and trace header (J12)
140 and J12 that can be used with Segger J-Link.
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| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/doc/ |
| D | index.rst | 53 17. PSOC 6 debug and trace header (J12)
153 and J12 that can be used with Segger J-Link [default].
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| /Zephyr-latest/boards/96boards/wistrio/doc/ |
| D | 96b_wistrio.rst | 144 - Connect BOOT0 to VDD (link pin 1 and 2 on J12)
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| /Zephyr-latest/samples/drivers/dac/ |
| D | README.rst | 223 DAC output is available on connector J12 pin 4.
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| /Zephyr-latest/boards/nxp/frdm_mcxw71/doc/ |
| D | index.rst | 113 10-pin SWD connector (J12) of the board.
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| /Zephyr-latest/boards/nxp/frdm_mcxn236/doc/ |
| D | index.rst | 151 10-pin SWD connector (J12) of the board. Additionally, the jumper JP7 must
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| /Zephyr-latest/boards/nxp/mimxrt1040_evk/doc/ |
| D | index.rst | 223 For the RT1040, J9/J10 are the SWD isolation jumpers, J12 is the DFU
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| /Zephyr-latest/boards/nxp/mimxrt1060_evk/doc/ |
| D | index.rst | 353 J12 is the DFU mode jumper, and the 20 pin JTAG/SWD header is present on J2.
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| /Zephyr-latest/boards/phytec/reel_board/doc/ |
| D | index.rst | 291 | J12 | closed solder jumper | testpoint DRDYn HDC1010 |
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