Searched full:fsync (Results 1 – 17 of 17) sorted by relevance
| /Zephyr-latest/lib/posix/options/ |
| D | Kconfig.sync_io | 8 bool "Support for fsync()"
10 Select 'y' here and Zephyr will provide an implementation of fsync().
13 https://pubs.opengroup.org/onlinepubs/9699919799/functions/fsync.html
20 Select 'y' here and Zephyr will provide an implementation of fdatasync(), fsync(),
35 Select 'y' here and Zephyr will provide an alias for fsync() as _fsync().
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| D | fsync.c | 12 int fsync(int fd) in fsync() function
17 FUNC_ALIAS(fsync, _fsync, int);
23 return fsync(fd); in fdatasync()
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| D | CMakeLists.txt | 78 zephyr_library_sources_ifdef(CONFIG_POSIX_FSYNC fsync.c)
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | dai.h | 52 /**< codec BLCK provider, codec FSYNC provider */
54 /**< codec BCLK consumer, codec FSYNC provider */
56 /**< codec BCLK provider, codec FSYNC consumer */
58 /**< codec BCLK consumer, codec FSYNC consumer */
71 DAI_PROTO_DSP_A, /**< TDM, FSYNC asserted 1 BCLK early */
72 DAI_PROTO_DSP_B, /**< TDM, FSYNC asserted at the same time as MSB */
79 * clock polarity (FSYNC/BCLK) compared to
83 /**< no BCLK inversion, no FSYNC inversion */
85 /**< no BCLK inversion, FSYNC inversion */
87 /**< BCLK inversion, no FSYNC inversion */
[all …]
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| /Zephyr-latest/drivers/dai/nxp/esai/ |
| D | esai.h | 235 /* FSYNC direction - input or output */
237 /* FSYNC polarity - LOW or HIGH */
240 /* should FSYNC be bit-wide or word-wide? */
247 /* should FSYNC be asserted before MSB transmission
252 /* FSYNC divison value - for network mode this is
498 LOG_DBG("FSYNC direction: %d", cfg->fsync_dir); in esai_dump_xceiver_config()
499 LOG_DBG("FSYNC polarity: %d", cfg->fsync_polarity); in esai_dump_xceiver_config()
501 LOG_DBG("FSYNC is bit wide: %d", cfg->fsync_is_bit_wide); in esai_dump_xceiver_config()
503 LOG_DBG("FSYNC asserted early: %d", cfg->fsync_early); in esai_dump_xceiver_config()
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| D | esai.c | 182 /* default FSYNC and BCLK are OUTPUT */ in esai_get_clk_provider_config()
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| /Zephyr-latest/drivers/dai/nxp/sai/ |
| D | Kconfig.sai | 37 the SAI is FSYNC/BCLK master, one of the directions
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| D | sai.c | 245 /* condition: BCLK = FSYNC * TDM_SLOT_WIDTH * TDM_SLOTS */ in sai_config_set()
285 /* FSYNC is asserted for tdm_slot_width BCLKs */ in sai_config_set()
320 /* FSYNC is active LOW */ in sai_config_set()
324 /* FSYNC is asserted for a single BCLK */ in sai_config_set()
359 LOG_DBG("FSYNC polarity: %d", tx_config->frameSync.frameSyncPolarity); in sai_config_set()
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| D | sai.h | 397 /* by default, FSYNC has the following properties: in get_fsync_default_config()
399 * 1) FSYNC is asserted one bit early with respect to the next in get_fsync_default_config()
401 * 2) FSYNC is active HIGH. in get_fsync_default_config()
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| /Zephyr-latest/tests/posix/fs/src/ |
| D | test_fs_file.c | 152 res = fsync(file); in test_file_fsync()
265 * @brief Test for POSIX fsync API
267 * @details Test sync the file through POSIX fsync API.
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| /Zephyr-latest/include/zephyr/posix/ |
| D | unistd.h | 35 int fsync(int fd);
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| /Zephyr-latest/dts/bindings/dai/ |
| D | nxp,dai-esai.yaml | 72 Use this property to configure the directions of the ESAI clocks (HCLK, BCLK, FSYNC).
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc3.h | 107 uint32_t fsync_rate; /* fsync frequency in Hz */
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_common.c | 205 /* Disable FSYNC */ in icm42688_configure()
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| /Zephyr-latest/doc/services/portability/posix/option_groups/ |
| D | index.rst | 733 fsync(),yes
897 fsync(),yes
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| /Zephyr-latest/subsys/fs/ |
| D | fuse_fs_access.c | 438 .fsync = NULL,
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| /Zephyr-latest/tests/posix/headers/src/ |
| D | unistd_h.c | 237 zassert_not_null(fsync); in ZTEST()
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