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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/
DKconfig.series2 # SPDX-License-Identifier: Apache-2.0
5 bool "ESP32-S2 Series"
18 Enable support for Espressif ESP32-S2
DKconfig.soc2 # SPDX-License-Identifier: Apache-2.0
15 prompt "ESP32-S2 SOC Selection"
65 - "Internal 90kHz oscillator" option provides lowest deep sleep current
69 - "External 32kHz crystal" provides better frequency stability, at the
71 - "External 32kHz oscillator" allows using 32kHz clock generated by an
78 - "Internal 8MHz oscillator divided by 256" option results in higher
114 - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
115 - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
186 menu "PSRAM clock and cs IO for ESP32-S2"
221 When using the default (Espressif-assigned) base MAC address, either setting can be used.
/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_franzininho/doc/
Dindex.rst3 ESP32-S2 Franzininho
9 …s an educational development board based on ESP32-S2 which is a highly integrated, low-power, sing…
10 designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities…
14 - RSA-3072-based secure boot
15 - AES-XTS-256-based flash encryption
16 - Protected private key and device secrets from software access
17 - Cryptographic accelerators for enhanced performance
18 - Protection against physical fault injection attacks
19 - Various peripherals:
21 - 43x programmable GPIOs
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/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_saola/doc/
Dindex.rst3 ESP32-S2 chapter
9 ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be s…
10 cost-effective, with a high performance and a rich set of IO capabilities. [1]_
14 - RSA-3072-based secure boot
15 - AES-XTS-256-based flash encryption
16 - Protected private key and device secrets from software access
17 - Cryptographic accelerators for enhanced performance
18 - Protection against physical fault injection attacks
19 - Various peripherals:
21 - 43x programmable GPIOs
[all …]
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Despressif,esp32-temp.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ESP32 family temperature sensor node
6 compatible: "espressif,esp32-temp"
8 include: sensor-device.yaml
14 The temperature sensor is available on the ESP32-S2, ESP32-C3. Note
15 that it is unavailable on the ESP32 due to missing offset calibration.
20 - 0 # measure range: 50°C ~ 125°C, error < 3°C
21 - 1 # measure range: 20°C ~ 100°C, error < 2°C
22 - 2 # measure range:-10°C ~ 80°C, error < 1°C
23 - 3 # measure range:-30°C ~ 50°C, error < 2°C
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/Zephyr-Core-3.5.0/dts/bindings/adc/
Despressif,esp32-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
6 Espressif ESP32 ADC
8 - ESP32 < 9,10,11,12 >
9 - ESP32-S2 < 12 >
10 - ESP32-C3 < 12 >
11 - ESP32-S3 < 12 >
12 For chips with configurable resolution feature (ESP32),
17 which coresponds to the ESP32 ADC attenuation feature.
19 ESP32,attenuation ~ zephyr,gain
20 ----------------- -----------
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/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_franzininho/
Desp32s2_franzininho.yaml2 name: ESP32-S2 Franzininho
6 - zephyr
8 - gpio
9 - i2c
10 - watchdog
11 - uart
12 - pinmux
13 - nvs
16 - heap
17 - net
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/Zephyr-Core-3.5.0/dts/bindings/dac/
Despressif,esp32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 is part of the RTC low-power domain and belongs to the SENSE
12 ESP32 pads
13 - GPIO25 as DAC channel 1
14 - GPIO26 as DAC channel 2
16 ESP32-S2 pads
17 - GPIO17 as DAC channel 1
18 - GPIO18 as DAC channel 2
28 properties 'dac-channel-id', which uses zero based channel index.
29 Variable 'dac-resolution' must be also specified, although ESP32
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/Zephyr-Core-3.5.0/boards/xtensa/esp32s2_saola/
Desp32s2_saola.yaml2 name: ESP32-S2 Saola
6 - zephyr
8 - adc
9 - dac
10 - gpio
11 - i2c
12 - watchdog
13 - uart
14 - nvs
15 - pwm
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/Zephyr-Core-3.5.0/samples/boards/esp32/spiram_test/
DREADME.rst3 Espressif ESP32 SPIRAM test
22 * ESP32
23 * ESP32-S2
30 .. code-block:: console
32 west build -b esp32_devkitc_wrover samples/boards/esp32/spiram_test
46 .. code-block:: console
50 .. code-block:: console
/Zephyr-Core-3.5.0/drivers/can/
Dcan_esp32_twai.c5 * SPDX-License-Identifier: Apache-2.0
23 * Newer ESP32-series MCUs like ESP32-C3 and ESP32-S2 have some slightly different registers
24 * compared to the original ESP32, which is fully compatible with the SJA1000 controller.
56 * - TWAI_STATUS_REG has new bit 8: TWAI_MISS_ST
57 * - TWAI_INT_RAW_REG has new bit 8: TWAI_BUS_STATE_INT_ST
58 * - TWAI_INT_ENA_REG has new bit 8: TWAI_BUS_STATE_INT_ENA
75 /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
82 const struct can_sja1000_config *sja1000_config = dev->config; in can_esp32_twai_read_reg()
83 const struct can_esp32_twai_config *twai_config = sja1000_config->custom; in can_esp32_twai_read_reg()
84 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_read_reg()
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/Zephyr-Core-3.5.0/drivers/adc/
Dadc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
30 * for ESP32-S2 is doing it, so we copy that approach in Zephyr driver
51 /* Convert resolution in bits to esp32 enum values */
52 #define WIDTH_MASK(r) ((((r) - 9) < ADC_WIDTH_MAX) ? ((r) - 9) : (ADC_WIDTH_MAX - 1))
76 /* Convert zephyr,gain property to the ESP32 attenuation */
93 return -ENOTSUP; in gain_to_atten()
122 struct adc_esp32_data *data = dev->data; in adc_calibration_init()
126 LOG_WRN("Skip software calibration - Not supported!"); in adc_calibration_init()
129 LOG_WRN("Skip software calibration - Invalid version!"); in adc_calibration_init()
143 const struct adc_esp32_conf *conf = dev->config; in adc_esp32_read()
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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Drelease-notes-2.4.rst33 * CVE-2020-10060: UpdateHub Might Dereference An Uninitialized Pointer
34 * CVE-2020-10064: Improper Input Frame Validation in ieee802154 Processing
35 * CVE-2020-10066: Incorrect Error Handling in Bluetooth HCI core
36 * CVE-2020-10072: all threads can access all socket file descriptors
37 * CVE-2020-13598: FS: Buffer Overflow when enabling Long File Names in FAT_FS and calling fs_stat
38 * CVE-2020-13599: Security problem with settings and littlefs
39 * CVE-2020-13601: Under embargo until 2020/11/18
40 * CVE-2020-13602: Remote Denial of Service in LwM2M do_write_op_tlv
50 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
62 * The :c:func:`wdt_feed` function will now return ``-EAGAIN`` if
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Drelease-notes-2.5.rst27 * CVE-2021-3323: Under embargo until 2021-04-14
28 * CVE-2021-3321: Under embargo until 2021-04-14
29 * CVE-2021-3320: Under embargo until 2021-04-14
39 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
56 * Changed vcnl4040 dts binding default for property 'proximity-trigger'.
63 * The :c:func:`mqtt_keepalive_time_left` function now returns -1 if keep alive
67 timeout usage must use the new-style k_timeout_t type and not the
87 GPIO-only regulators a devicetree property ``supply-gpios`` is defined as a
101 * ARM Musca-A board and SoC support deprecated and planned to be removed in 2.6.0.
146 sys_heap/k_heaps. Note that the new-style heap is a general
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32/
Ddefault.ld5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/linker/linker-defs.h>
18 #include <zephyr/linker/linker-tool.h>
40 #define IROM_SEG_LEN FLASH_SIZE-0x20
58 ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
68 * Following is DRAM memory split with reserved address ranges in ESP32:
70 * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions)
71 * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)
72 * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU)
73 * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU)
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s3/
Ddefault.ld3 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/linker/linker-defs.h>
16 #include <zephyr/linker/linker-tool.h>
23 #define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
26 #define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
27 #define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
31 #define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
44 #define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE)
54 #define IROM_SEG_LEN FLASH_SIZE-0x20
79 ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
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/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
Ddefault.ld3 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/linker/linker-defs.h>
16 #include <zephyr/linker/linker-tool.h>
27 #define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
28 #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
31 #define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET
34 #define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
44 #define IROM_SEG_LEN (FLASH_SIZE-0x20)
62 ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
67 drom0_0_seg (R) : org = 0x3C000040, len = FLASH_SIZE - 0x40
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