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/Zephyr-Core-3.5.0/lib/os/
Ddec.c11 uint8_t divisor = 100; in u8_to_dec() local
15 while ((buflen > 0) && (divisor > 0)) { in u8_to_dec()
16 digit = value / divisor; in u8_to_dec()
17 if ((digit != 0) || (divisor == 1) || (num_digits != 0)) { in u8_to_dec()
24 value -= digit * divisor; in u8_to_dec()
25 divisor /= 10; in u8_to_dec()
/Zephyr-Core-3.5.0/drivers/sensor/vl53l1x/
Dvl53l1_platform_user_defines.h29 * @param divisor unsigned 64-bit denominator
31 #define do_division_u(dividend, divisor) (dividend / divisor) argument
39 * @param divisor signed 64-bit denominator
41 #define do_division_s(dividend, divisor) (dividend / divisor) argument
/Zephyr-Core-3.5.0/include/zephyr/bluetooth/mesh/
Dhealth_cli.h43 * server. The @c divisor param represents the period divisor value.
47 * @param divisor Health Period Divisor value.
50 uint8_t divisor);
217 /** @brief Get the target node's Health fast period divisor.
219 * The health period divisor is used to increase the publish rate when a fault
222 * period is divided by (1 << divisor). For example, if the target node's
224 * Health fast period divisor is 5, the Health server will publish with an
227 * This method can be used asynchronously by setting @p divisor
237 * @param divisor Health period divisor response buffer.
242 uint8_t *divisor);
[all …]
/Zephyr-Core-3.5.0/soc/arc/snps_arc_iot/
Dsysconf.h19 volatile uint32_t AHBCLKDIV; /* AHB clock divisor */
20 volatile uint32_t APBCLKDIV; /* APB clock divisor */
22 volatile uint32_t CLKODIV; /* AHB clock output enable and divisor set */
26 volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */
33 volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */
34 volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */
36 volatile uint32_t SDIO_REFCLK_DIV; /* SDIO reference clock divisor */
37 volatile uint32_t GPIO4B_DBCLK_DIV; /* GPIO4B DBCLK divisor */
40 volatile uint32_t SPI_MST_CLKDIV; /* SPI master clock divisor */
50 volatile uint32_t GPIO8B_DBCLK_DIV; /* GPIO8B DBCLK divisor */
/Zephyr-Core-3.5.0/subsys/bluetooth/mesh/
Dhealth_cli.c117 uint8_t *divisor; member
126 uint8_t divisor; in health_period_status() local
131 divisor = net_buf_simple_pull_u8(buf); in health_period_status()
136 if (param->divisor) { in health_period_status()
137 *param->divisor = divisor; in health_period_status()
144 cli->period_status(cli, ctx->addr, divisor); in health_period_status()
243 uint8_t *divisor) in bt_mesh_health_cli_period_get() argument
247 .divisor = divisor, in bt_mesh_health_cli_period_get()
259 return bt_mesh_msg_ackd_send(cli->model, ctx, &msg, divisor ? &rsp : NULL); in bt_mesh_health_cli_period_get()
263 uint8_t divisor, uint8_t *updated_divisor) in bt_mesh_health_cli_period_set() argument
[all …]
/Zephyr-Core-3.5.0/tests/kernel/fpu_sharing/generic/src/
Dpi.c76 FP_TYPE divisor = FP_CONSTANT(3.0); in calculate_pi_low() local
85 divisor = FP_CONSTANT(3.0); in calculate_pi_low()
88 pi += sign / divisor; in calculate_pi_low()
89 divisor += FP_CONSTANT(2.0); in calculate_pi_low()
115 FP_TYPE divisor = FP_CONSTANT(3.0); in calculate_pi_high() local
126 divisor = FP_CONSTANT(3.0); in calculate_pi_high()
129 pi += sign / divisor; in calculate_pi_high()
130 divisor += FP_CONSTANT(2.0); in calculate_pi_high()
/Zephyr-Core-3.5.0/drivers/sdhc/
DKconfig.sam_hsmci30 int "Divisor value of clock when in power-save mode"
34 is the divisor value. Valid values are 0 to 7.
/Zephyr-Core-3.5.0/subsys/bluetooth/mesh/shell/
Dhealth.c185 uint8_t divisor; in cmd_period_get() local
188 err = bt_mesh_health_cli_period_get(cli, ctx.addr ? &ctx : NULL, &divisor); in cmd_period_get()
192 shell_print(sh, "Health FastPeriodDivisor: %u", divisor); in cmd_period_get()
207 uint8_t divisor; in period_set() local
210 divisor = shell_strtoul(argv[1], 0, &err); in period_set()
219 err = bt_mesh_health_cli_period_set(cli, ctx.addr ? &ctx : NULL, divisor, in period_set()
230 err = bt_mesh_health_cli_period_set_unack(cli, ctx.addr ? &ctx : NULL, divisor); in period_set()
332 SHELL_CMD_ARG(period-set, NULL, "<Divisor>", cmd_period_set, 2, 0),
333 SHELL_CMD_ARG(period-set-unack, NULL, "<Divisor>", cmd_period_set_unack, 2, 0),
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc11u6x/
Dsoc.h35 * [13:15] clock divisor.
67 * [13:15] clock divisor.
86 * [13:15] clock divisor.
/Zephyr-Core-3.5.0/arch/x86/core/
Dearly_serial.c51 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
52 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
106 OUT(REG_BRDL, 1); /* Baud divisor = 1 */ in z_x86_early_serial_init()
/Zephyr-Core-3.5.0/dts/bindings/serial/
Daltr,uart.yaml19 Baud rate cannot be changed by software (Divisor register is not writable)
Dns16550.yaml19 description: divisor latch fraction (DLF, if supported)
/Zephyr-Core-3.5.0/dts/bindings/clock/
Despressif,esp32-rtc.yaml21 description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div
Dst,stm32c0-hsi-clock.yaml9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
Dst,stm32f1-pll-clock.yaml43 Otpional PLL output divisor to generate a 48MHz USB clock.
Dst,stm32g0-hsi-clock.yaml9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
Dst,stm32f105-pll-clock.yaml58 Otpional PLL output divisor to generate a 48MHz USB clock.
/Zephyr-Core-3.5.0/dts/bindings/can/
Dst,stm32-fdcan.yaml40 Note that the divisor is common to all 'st,stm32-fdcan' instances.
/Zephyr-Core-3.5.0/dts/bindings/adc/
Datmel,sam0-adc.yaml33 description: clock prescaler divisor applied to the generic clock
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_ite_it8xxx2.c160 * 2) CxCPRS[15:0] value 0001h results in a divisor 2 in pwm_it8xxx2_set_cycles()
161 * CxCPRS[15:0] value FFFFh results in a divisor 65536 in pwm_it8xxx2_set_cycles()
162 * CTRx[7:0] value 00h results in a divisor 1 in pwm_it8xxx2_set_cycles()
163 * CTRx[7:0] value FFh results in a divisor 256 in pwm_it8xxx2_set_cycles()
/Zephyr-Core-3.5.0/soc/arm/quicklogic_eos_s3/
Dsoc.c40 /* Turn off divisor for A0 domain */ in eos_s3_cru_init()
/Zephyr-Core-3.5.0/subsys/net/lib/zperf/
Dzperf_shell.c88 const uint32_t *divisor; in print_number() local
92 divisor = divisor_arr; in print_number()
94 while (value < *divisor) { in print_number()
95 divisor++; in print_number()
99 if (*divisor != 0U) { in print_number()
100 radix = value / *divisor; in print_number()
101 dec = (value % *divisor) * 100U / *divisor; in print_number()
113 const uint32_t *divisor; in parse_number() local
120 divisor = divisor_arr; in parse_number()
124 } while (cmp != 0 && *++divisor != 0U); in parse_number()
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/Zephyr-Core-3.5.0/drivers/serial/
Duart_mchp_xec.c54 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
55 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
140 #define LCR_DLAB 0x80 /* divisor latch access enable */
293 uint32_t divisor; /* baud rate divisor */ in set_baud_rate() local
298 * calculate baud rate divisor. a variant of in set_baud_rate()
301 divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3)) in set_baud_rate()
304 /* set the DLAB to access the baud rate divisor registers */ in set_baud_rate()
307 regs->RTXB = (unsigned char)(divisor & 0xff); in set_baud_rate()
309 regs->IER = (unsigned char)((divisor >> 8) & 0x7f); in set_baud_rate()
311 /* restore the DLAB to access the baud rate divisor registers */ in set_baud_rate()
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Dadsp_shim.h108 #define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
109 #define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_uart.h24 * LCR DLAB=1, BAUD rate divisor LSB
32 * LCR DLAB=1, BAUD rate divisor MSB

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