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12

/Zephyr-Core-3.5.0/soc/arc/snps_nsim/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 prompt "ARC nSIM SoC Selection"
10 bool "Synopsys ARC EM in nSIM"
14 bool "Synopsys ARC EM7D_V22 in nSIM"
19 bool "Synopsys ARC EM11D in nSIM"
24 bool "Synopsys ARC SEM in nSIM"
30 bool "Synopsys ARC HS in nSIM"
35 bool "Multi-core Synopsys ARC HS in nSIM"
39 bool "Synopsys ARC HS with MPU v6 in nSIM"
44 bool "Synopsys ARC VPX5 in nSIM"
[all …]
DKconfig.defconfig2 # SPDX-License-Identifier: Apache-2.0
12 source "soc/arc/snps_nsim/Kconfig.defconfig.em"
13 source "soc/arc/snps_nsim/Kconfig.defconfig.em11d"
14 source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22"
15 source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
16 source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
17 source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"
18 source "soc/arc/snps_nsim/Kconfig.defconfig.vpx5"
19 source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x"
20 source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp"
[all …]
/Zephyr-Core-3.5.0/boards/arc/hsdk/
DKconfig.board1 # DesignWare ARC HS Development Kit board configuration
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ARC HS Development Kit"
10 The DesignWare ARC HS Development Kit is a ready-to-use platform for
11 rapid software development on the ARC HS3x family of processors. It
12 supports single- and multi-core ARC HS34, HS36 and HS38 processors
Dhsdk.yaml2 name: HS Development Kit
4 arch: arc
6 - zephyr
7 - cross-compile
8 - xtools
9 - arcmwdt
11 - smp
14 - net
15 - bluetooth
Dhsdk_2cores.yaml2 name: HS Development Kit(2 cores)
4 arch: arc
6 - zephyr
7 - cross-compile
8 - xtools
9 - arcmwdt
11 - smp
14 - net
15 - bluetooth
/Zephyr-Core-3.5.0/soc/arc/snps_qemu/
DKconfig.defconfig2 # SPDX-License-Identifier: Apache-2.0
26 # Technically ARC HS supports MPUv3, but not v2. But given MPUv3
33 source "soc/arc/snps_qemu/Kconfig.defconfig.em"
34 source "soc/arc/snps_qemu/Kconfig.defconfig.hs"
35 source "soc/arc/snps_qemu/Kconfig.defconfig.hs5x"
36 source "soc/arc/snps_qemu/Kconfig.defconfig.hs6x"
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 prompt "ARC QEMU SoC Selection"
10 bool "Synopsys ARC EM in QEMU"
13 bool "Synopsys ARC HS in QEMU"
16 bool "Synopsys ARC HS6x in QEMU"
19 bool "Synopsys ARC HS5x in QEMU"
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
4 zephyr_compile_options(-mcpu=${GCC_M_CPU})
6 zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata)
10 zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic
11 -Xunaligned -Xcode_density -Xswap -Xbitscan
12 -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter
13 -Xtimer0 -Xtimer1)
15 zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full)
18 message(WARNING "QEMU ARC platforms other than HS are not supported yet with MW toolchain")
/Zephyr-Core-3.5.0/boards/arc/hsdk/support/
Dopenocd-2-cores.cfg2 # SPDX-License-Identifier: Apache-2.0
6 # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
28 # HS Development Kit SoC.
30 # Contains quad-core ARC HS38.
33 source [find cpu/arc/hs.tcl]
39 # OpenOCD is concerned EM and HS are identical.
40 set _CHIPNAME arc-em
45 jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
47 jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
49 jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
[all …]
Dopenocd.cfg1 # Copyright (C) 2019-2020 Synopsys, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
28 # HS Development Kit SoC.
30 # Contains quad-core ARC HS38.
33 source [find cpu/arc/hs.tcl]
39 # OpenOCD is concerned EM and HS are identical.
40 set _CHIPNAME arc-em
45 jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
47 jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
[all …]
/Zephyr-Core-3.5.0/boards/arc/hsdk4xd/support/
Dopenocd.cfg1 # Copyright (C) 2019-2023 Synopsys, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
28 # HS Development Kit SoC.
30 # Contains quad-core ARC HS4x.
33 source [find cpu/arc/hs.tcl]
39 # OpenOCD is concerned EM and HS are identical.
40 set _CHIPNAME arc-em
45 jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x100c54b1
47 jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x100854b1
[all …]
/Zephyr-Core-3.5.0/boards/arc/qemu_arc/
Dqemu_arc_hs6x.yaml2 name: QEMU Emulation for ARC HS
5 arch: arc
7 - cross-compile
8 - zephyr
12 - net
13 - bluetooth
Dqemu_arc_hs_xip.yaml2 name: QEMU Emulation for ARC HS
5 arch: arc
7 - zephyr
8 - cross-compile
12 - net
13 - bluetooth
Dqemu_arc_hs.yaml2 name: QEMU Emulation for ARC HS
5 arch: arc
7 - zephyr
8 - cross-compile
9 - arcmwdt
13 - net
14 - bluetooth
DKconfig.board3 # SPDX-License-Identifier: Apache-2.0
6 bool "ARC QEMU for EM & HS cores"
Dqemu_arc_hs6x.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
12 model = "QEMU ARC HS";
13 compatible = "snps,qemu-archs";
16 #address-cells = <1>;
17 #size-cells = <0>;
/Zephyr-Core-3.5.0/boards/arc/nsim/doc/
Dindex.rst3 DesignWare ARC nSIM and HAPS FPGA boards
9 This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in
10 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
13 * ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to
14 :ref:`here <hardware_arch_arc_support_status>` for a complete list of ARC processor families which
18 ARC processors are known for being highly customizable and some but not all of the configurations
19 are currently supported in the Zephyr RTOS for ARC, again please refer to
22 There are multiple supported sub-configurations for that platform. Some but not all of currently
25 * ``nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
26 XY-memory
[all …]
/Zephyr-Core-3.5.0/boards/arc/nsim/
Dnsim_hs.yaml2 name: HS nSIM simulator
6 arch: arc
8 - zephyr
9 - cross-compile
10 - arcmwdt
13 - net
14 - bluetooth
Dnsim_hs_flash_xip.yaml2 name: HS nSIM simulator
6 arch: arc
8 - zephyr
9 - cross-compile
10 - arcmwdt
13 - net
14 - bluetooth
Dnsim_hs_sram.yaml2 name: HS nSIM simulator
6 arch: arc
8 - zephyr
9 - cross-compile
10 - arcmwdt
13 - net
14 - bluetooth
Dnsim_hs_mpuv6.yaml2 name: HS (with MPU v6) nSIM simulator
6 arch: arc
8 - zephyr
9 - cross-compile
10 - arcmwdt
14 - net
15 - bluetooth
Dnsim_hs_smp.yaml2 name: Multi-core HS nSIM simulator
4 simulation: mdb-nsim
6 arch: arc
8 - zephyr
9 - cross-compile
10 - arcmwdt
12 - smp
17 - net
18 - bluetooth
/Zephyr-Core-3.5.0/boards/arc/iotdk/support/
Dopenocd.cfg2 # SPDX-License-Identifier: Apache-2.0
6 # Synopsys DesignWare ARC IoT Development Kit
10 # IoT DK has built-in FT2232 chip, which is similar to Digilent HS-1.
30 source [find cpu/arc/em.tcl]
32 set _CHIPNAME arc-em
36 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1
41 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
42 -coreid 0 -dbgbase $_dbgbase -endian little
45 $_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
/Zephyr-Core-3.5.0/boards/arc/emsdp/support/
Dopenocd.cfg2 # SPDX-License-Identifier: Apache-2.0
6 # Synopsys DesignWare ARC EM Software Development Platform
10 # EM SDP has built-in FT2232 chip, which is similar to Digilent HS-1.
30 source [find cpu/arc/em.tcl]
32 set _CHIPNAME arc-em
36 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200044b1
41 target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
42 -coreid 0 -dbgbase $_dbgbase -endian little
45 $_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
/Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/
Dsnps,archs-idu-intc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
9 compatible: "snps,archs-idu-intc"
11 include: [interrupt-controller.yaml, base.yaml]
13 interrupt-cells:
14 - irq
15 - priority

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