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/Zephyr-Core-3.5.0/arch/xtensa/core/
Ddebug_helpers_asm.S24 * Use a6 and a7 as scratch */
27 l32i a6, a5, 0
29 l32i a7, a6, ___xtensa_irq_bsa_t_pc_OFFSET
33 l32i a7, a6, ___xtensa_irq_bsa_t_a0_OFFSET
37 addi a6, a6, ___xtensa_irq_bsa_t_SIZEOF
39 s32i a6, a3, 0
Dcrt1.S42 # define ARG5 a6 /* 5th outgoing call argument */
46 # define ARG1 a6 /* 1st outgoing call argument */
161 * a6 = pointer to start of table, and through table
167 movi a6, _bss_table_start
169 bgeu a6, a7, .L3zte
171 .L0zte: l32i a8, a6, 0 /* get start address, assumed multiple of 4 */
172 l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
173 addi a6, a6, 8 /* next entry */
191 bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
Dwindow_vectors.S141 s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
170 l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
199 s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
232 l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
Dcoredump.c70 uint32_t a6; member
160 arch_blk.r.a6 = frame->blks[regs_blk_remaining].r2; in arch_coredump_info_dump()
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h21 unsigned long a6; member
43 unsigned long a6, unsigned long a7,
56 unsigned long a6, unsigned long a7,
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-mkr-header.yaml10 A1 to A6 is Analog input. The outside pin is AREF.
19 correspond to A0 through A6, as depicted below.
28 21 A6/D21 D12/SCL 12
Darduino-nano-header-r3.yaml24 3 D3 A6/D20 20
/Zephyr-Core-3.5.0/arch/riscv/core/
Dcoredump.c26 uint32_t a6; member
78 arch_blk.r.a6 = esf->a6; in arch_coredump_info_dump()
Dfatal.c46 LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6); in z_riscv_fatal_error()
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-context.h49 * - Saved A6 |
179 uintptr_t a6; member
200 uintptr_t a6; member
216 uintptr_t a6; member
Dxtensa-asm2-s.h350 mov a6, a3 /* place "new sp" in the next frame's A2 */
362 mov a2, a6 /* copy return value */
375 mov a2, a6 /* copy return value */
380 * handler pointer is still in A6 (not A2) even though this is
491 * to restore to in A6 (the call4'd function's A2). If this
498 beq a6, a1, _restore_\@
508 mov a1, a6
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
102 #define DEFINE_TEST_VARIANT6(name, variant, a1, a2, a3, a4, a5, a6) \ argument
105 test_##name(a1, a2, a3, a4, a5, a6); \
108 #define DEFINE_TEST_VARIANT7(name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
111 test_##name(a1, a2, a3, a4, a5, a6, a7); \
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/
Dxtensa.py290 A6 = 95 variable in GdbRegDef_Sample_Controller.RegNum
324 A6 = 163 variable in GdbRegDef_ESP32.RegNum
356 A6 = 161 variable in GdbRegDef_ESP32S2.RegNum
386 A6 = 218 variable in GdbRegDef_ESP32S3.RegNum
427 A6 = 164 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
467 A6 = 262 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
502 A6 = 111 variable in GdbRegDef_DC233C.RegNum
Drisc_v.py34 A6 = 16 variable in RegNum
84 self.registers[RegNum.A6] = tu[11]
/Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
263 * @param a6 Argument 6 for supervisory call.
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
291 __ASSERT(a6, "a6 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
/Zephyr-Core-3.5.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c119 unsigned long *a4, unsigned long *a5, unsigned long *a6, in intel_sip_smc_plat_async_res_req() argument
201 LOG_DBG("\tres->a6 %08lx", res->a6); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.5.0/doc/develop/test/
Dtwister_and_pytest.svg4 …a6" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-event…
/Zephyr-Core-3.5.0/boards/arm/adafruit_kb2040/
Dsparkfun_pro_micro_connector.dtsi18 , <4 0 &gpio0 4 0> /* D4/A6 */
/Zephyr-Core-3.5.0/boards/arm/sparkfun_pro_micro_rp2040/
Dsparkfun_pro_micro_connector.dtsi18 , <4 0 &gpio0 4 0> /* D4/A6 */
/Zephyr-Core-3.5.0/boards/arm/nucleo_l031k6/
Darduino_nano_r3_connector.dtsi32 <20 0 &gpioa 7 0>, /* D20 / A6 */
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S402 movi a6, 8
424 addi a6, a6, -1
425 add a5, a5, a6 /* add the index */
427 bnez a6, 2b /* loop until done */
488 uploop: l32i a6, a5, 0
490 s32i a6, a3, 0
/Zephyr-Core-3.5.0/boards/arm/actinius_icarus/
Dfeather_connector.dtsi18 <5 0 &gpio0 19 0>, /* A6 */
/Zephyr-Core-3.5.0/boards/arm/nrf52_adafruit_feather/
Dfeather_connector.dtsi28 <15 0 &gpio0 30 0>, /* A6 */
/Zephyr-Core-3.5.0/samples/tfm_integration/psa_crypto/
DREADME.rst272 00000050 EE FF 3A 00 01 24 FB 58 20 A0 A1 A2 A3 A4 A5 A6 ..:..$.X .......
328 00000000 EE F1 FE A6 A8 41 5F CC A6 3A 73 A7 C1 33 B4 78 .....A_..:s..3.x
330 00000020 A6 22 2C 64 7A C7 E4 0A FB 99 D1 8B 67 37 F7 13 .",dz.......g7..
340 00000010 27 AC C2 42 59 15 5E 3C EB 11 20 3C 14 A6 EB 60 '..BY.^<.. <...`
349 000000A0 D7 BF 50 60 6C 65 8A 7C A6 CD C5 98 8B 15 EA F0 ..P`le.|........
/Zephyr-Core-3.5.0/boards/arm/nucleo_g031k8/
Darduino_nano_r3_connector.dtsi32 <20 0 &gpioa 6 0>, /* D20 / A6 */

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