Searched full:45 (Results 1 – 25 of 249) sorted by relevance
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| /Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam3x/ |
| D | Kconfig.defconfig.series | 21 # SAM3 family has total 45 peripherals capable of
25 default 45
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | mdio.h | 50 /** Read data from MDIO bus using Clause 45 access */
54 /** Write data to MDIO bus using Clause 45 access */
160 * @brief Read from MDIO Bus using Clause 45 access
163 * IEEE 802.3 Clause 45 access.
174 * @retval -ENOSYS if write using Clause 45 access is not supported
194 * @brief Write to MDIO bus using Clause 45 access
197 * IEEE 802.3 Clause 45 access.
208 * @retval -ENOSYS if write using Clause 45 access is not supported
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | quicklogic-eos-s3-pinctrl.h | 13 #define IO_MUX_MAX_PAD_NR 45
20 #define UART_RX_PAD45 QUICKLOGIC_EOS_S3_PINMUX(45, FUNC_SEL_UART_RX | BIT(2))
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| D | ti-cc32xx-pinctrl.h | 141 #define GPIO31_P45 TI_CC32XX_PINMUX(45U, 0U)
142 #define UART0_RX_P45 TI_CC32XX_PINMUX(45U, 9U)
143 #define MCAFSX_P45 TI_CC32XX_PINMUX(45U, 12U)
144 #define UART1_RX_P45 TI_CC32XX_PINMUX(45U, 2U)
145 #define MCAXR0_P45 TI_CC32XX_PINMUX(45U, 6U)
146 #define GSPI_CLK_P45 TI_CC32XX_PINMUX(45U, 7U)
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| /Zephyr-Core-3.5.0/tests/drivers/rtc/shell/src/ |
| D | main.c | 149 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 23:45:16"); in ZTEST()
153 assert_set_time(2023, 12, 24, 23, 45, 16); in ZTEST()
164 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 2022-05-17T23:45:16"); in ZTEST()
168 assert_set_time(2022, 5, 17, 23, 45, 16); in ZTEST()
179 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 2022:05:17T23:45:16"); in ZTEST()
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | nxp,imx8m-pinctrl.yaml | 80 - "45-ohm"
93 110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
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| /Zephyr-Core-3.5.0/samples/subsys/logging/dictionary/ |
| D | README.rst | 74 … 48 45 58 44 55 4d 50 21 20 48 45 58 44 55 4d 50 |HEXDUMP! HEXDUMP
75 40 20 48 45 58 44 55 4d 50 23 |@ HEXDUM P#
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/ |
| D | Kconfig | 6 default 45
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt685_evk/ |
| D | Kconfig | 6 default 45
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| /Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32l1/ |
| D | Kconfig.defconfig.stm32l151xb | 12 default 45
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| D | Kconfig.defconfig.stm32l151x8a | 12 default 45
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| D | Kconfig.defconfig.stm32l151xba | 12 default 45
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| /Zephyr-Core-3.5.0/drivers/regulator/ |
| D | Kconfig.nxp_vref | 12 default 45
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| /Zephyr-Core-3.5.0/soc/arm/silabs_exx32/efr32fg13p/ |
| D | Kconfig.defconfig.series | 16 default 45
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| /Zephyr-Core-3.5.0/tests/unit/timeutil/ |
| D | test_s64.c | 16 .civil = "1901-12-13 20:45:52 Fri 347",
19 .tm_min = 45,
28 .civil = "1901-12-13 20:45:51 Fri 347",
31 .tm_min = 45,
272 .civil = "1901-12-13 20:45:51 Fri 347", in test_time32_underflow()
275 .tm_min = 45, in test_time32_underflow()
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| /Zephyr-Core-3.5.0/soc/arm/arm/beetle/ |
| D | Kconfig.defconfig.series | 14 default 45
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| /Zephyr-Core-3.5.0/dts/bindings/input/ |
| D | zephyr,input-longpress.yaml | 34 input event: dev=longpress SYN type= 1 code= 45 value=1 # INPUT_KEY_X press
37 input event: dev=longpress SYN type= 1 code= 45 value=0 # INPUT_KEY_X release
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| /Zephyr-Core-3.5.0/drivers/can/transceiver/ |
| D | Kconfig | 10 default 45
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| /Zephyr-Core-3.5.0/boards/arm/thingy52_nrf52832/ |
| D | thingy52_nrf52832_defconfig | 22 CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45
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| /Zephyr-Core-3.5.0/boards/arm/mimx8mq_evk/ |
| D | mimx8mq_evk-pinctrl.dtsi | 17 drive-strength = "45-ohm";
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.shared_irq | 17 default 45
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| /Zephyr-Core-3.5.0/tests/drivers/coredump/coredump_api/ |
| D | testcase.yaml | 19 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
44 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 153 #define MIO45 45
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
202 #define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
238 #define MIO_GROUP_CAN1_9_GRP_PINS 44, 45
261 #define MIO_GROUP_UART1_9_GRP_PINS 44, 45
283 #define MIO_GROUP_I2C1_8_GRP_PINS 44, 45
342 #define MIO_GROUP_GPIO0_45_GRP_PINS 45
352 #define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
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| /Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/ |
| D | mr_canhubk3.overlay | 10 dmas = <&edma0 10 45>, <&edma0 12 46>;
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| /Zephyr-Core-3.5.0/tests/subsys/debug/coredump/ |
| D | testcase.yaml | 16 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
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