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/Zephyr-Core-3.5.0/samples/net/gptp/
DREADME.rst1 .. zephyr:code-sample:: gptp
3 :relevant-api: gptp ptp_time
5 Enable gPTP support and monitor functionality using net-shell.
12 queues) and setup VLANs (if enabled). The net-shell is also enabled so that
29 embedded device like NXP FRDM-K64F, Nucleo-H743-ZI, Nucleo-H745ZI-Q,
30 Nucleo-F767ZI or Atmel SAM-E70 Xplained. Note that gPTP is only supported for
36 .. zephyr-app-commands::
37 :zephyr-app: samples/net/gptp
42 The net-shell command "**net gptp**" will print out general gPTP information.
52 :zephyr_file:`samples/net/vlan/vlan-setup-linux.sh` provides a script that can be
[all …]
/Zephyr-Core-3.5.0/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
45 IPC_EVENT_BIT(13) | \
46 IPC_EVENT_BIT(14) | \
65 [13] = BIT(13),
66 [14] = BIT(14),
83 [13] = BIT(13),
84 [14] = BIT(14),
/Zephyr-Core-3.5.0/boards/arm/rak5010_nrf52840/
Drak5010_nrf52840-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
22 low-power-enable;
37 low-power-enable;
43 psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
44 <NRF_PSEL(TWIM_SCL, 0, 13)>;
50 psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
51 <NRF_PSEL(TWIM_SCL, 0, 13)>;
52 low-power-enable;
60 <NRF_PSEL(QSPI_IO1, 1, 14)>,
61 <NRF_PSEL(QSPI_IO2, 1, 13)>,
[all …]
/Zephyr-Core-3.5.0/boards/arm/stm32mp157c_dk2/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpiof 14 0>, /* A0 */
14 <1 0 &gpiof 13 0>, /* A1 */
22 <9 0 &gpiod 14 0>, /* D3 */
26 <13 0 &gpiod 1 0>, /* D7 */
27 <14 0 &gpiog 3 0>, /* D8 */
[all …]
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
36 #define APL_GPIO_13 13
37 #define APL_GPIO_14 14
70 #define APL_GPIO_45 13
71 #define APL_GPIO_46 14
104 #define APL_GPIO_SVOD0_CLK 13
120 #define APL_GPIO_200 13
121 #define APL_GPIO_201 14
154 #define APL_GPIO_85 13
[all …]
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dst,stm32u5-msi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32u5-msi-clock"
9 - name: st,stm32-msi-clock.yaml
10 property-blocklist:
11 - msi-range
15 msi-range:
22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f429zi/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f412zg/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f413zh/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f446ze/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f746zg/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f756zg/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f767zi/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f207zg/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpiog 14 0>, /* D1 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
[all …]
/Zephyr-Core-3.5.0/samples/tfm_integration/tfm_secure_partition/dummy_partition/
Ddummy_partition.c4 * SPDX-License-Identifier: Apache-2.0
22 { {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
23 { {1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
24 { {2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
25 { {3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
26 { {4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
78 if (msg->in_size[0] != sizeof(secret_index)) { in tfm_dp_secret_digest_ipc()
83 num = psa_read(msg->handle, 0, &secret_index, msg->in_size[0]); in tfm_dp_secret_digest_ipc()
84 if (num != msg->in_size[0]) { in tfm_dp_secret_digest_ipc()
88 return tfm_dp_secret_digest(secret_index, msg->out_size[0], in tfm_dp_secret_digest_ipc()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
26 #define PIN_D13 RCAR_GP_PIN(0, 13)
27 #define PIN_D14 RCAR_GP_PIN(0, 14)
42 #define PIN_A13 RCAR_GP_PIN(1, 13)
43 #define PIN_A14 RCAR_GP_PIN(1, 14)
71 #define PIN_AVB_AVTP_MATCH_A RCAR_GP_PIN(2, 13)
72 #define PIN_AVB_AVTP_CAPTURE_A RCAR_GP_PIN(2, 14)
86 #define PIN_SD0_WP RCAR_GP_PIN(3, 13)
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/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_hogs/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 output-high-gpios = <&gpio_000_036 13 GPIO_ACTIVE_LOW>;
12 output-low-gpios = <&gpio_000_036 14 GPIO_ACTIVE_HIGH>;
13 input-gpios = <&gpio_000_036 11 GPIO_ACTIVE_LOW>;
19 gpio-hog;
20 gpios = <13 GPIO_ACTIVE_LOW>;
21 output-high;
25 gpio-hog;
26 gpios = <14 GPIO_ACTIVE_HIGH>;
[all …]
Dnrf52840dk_nrf52840.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 output-high-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
12 output-low-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
13 input-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
19 gpio-hog;
20 gpios = <13 GPIO_ACTIVE_LOW>;
21 output-high;
25 gpio-hog;
26 gpios = <14 GPIO_ACTIVE_HIGH>;
[all …]
Dnrf52_bsim.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 output-high-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
12 output-low-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
13 input-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
19 gpio-hog;
20 gpios = <13 GPIO_ACTIVE_LOW>;
21 output-high;
25 gpio-hog;
26 gpios = <14 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
43 1 = /2 -> ±80 mV
[all …]
/Zephyr-Core-3.5.0/boards/arm/nrf5340dk_nrf5340/
Dnrf5340_cpuapp_common-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
30 bias-pull-up;
40 low-power-enable;
53 low-power-enable;
60 <NRF_PSEL(QSPI_IO0, 0, 13)>,
61 <NRF_PSEL(QSPI_IO1, 0, 14)>,
65 nordic,drive-mode = <NRF_DRIVE_H0H1>;
72 <NRF_PSEL(QSPI_IO0, 0, 13)>,
73 <NRF_PSEL(QSPI_IO1, 0, 14)>,
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_l552ze_q/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
22 <9 0 &gpioe 13 0>, /* D3 */
23 <10 0 &gpiof 14 0>, /* D4 */
26 <13 0 &gpiof 13 0>, /* D7 */
27 <14 0 &gpiof 12 0>, /* D8 */
[all …]
/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
57 #define REFLECT {1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, \
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/boards/arm/nucleo_h563zi/
Dst_morpho_connector.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
21 <ST_MORPHO_L_13 0 &gpioa 13 0>,
[all …]
/Zephyr-Core-3.5.0/boards/arm/stm32h7b3i_dk/
Darduino_r3_connector.dtsi2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 4 0>, /* A0 */
19 <6 0 &gpioh 14 0>, /* D0 */
20 <7 0 &gpioh 13 0>, /* D1 */
26 <13 0 &gpioi 10 0>, /* D7 */
[all …]

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