| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
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| D | digilent,pmod.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
25 6-pin Pmod interface:
31 - GND
32 - VDD
[all …]
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| D | adafruit-feather-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
24 1 A1 - EN
[all …]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
41 8 I2C(SDA) 11 12 I2C(SCL) 9
43 12 SPI(CS0) 15 16 SPI(MOSI) 13
[all …]
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| D | sparkfun-pro-micro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 Proceeding counter-clockwise:
11 * A 12-pin Power and Digital Input header. This has input signals
13 * An 12-pin Power and Digital/Analog Input header. This
15 non-monotonically decreasing numbering.
19 0 TX0 RAW -
20 1 RX1 GND -
21 - GND RST -
22 - GND VCC -
33 compatible: "sparkfun,pro-micro-gpio"
[all …]
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| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
25 9 I2C SCL 29 32 GPIO 12 GPIO / SPI CS
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| D | arduino-mkr-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
23 16 A1/D16 VCC -
[all …]
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/adc/adc_api/boards/ |
| D | lpcxpresso55s69_cpu0.overlay | 2 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 * Channel 0 is used in single ended mode, with 12 bit resolution
21 * CH0A is routed to P19 pin 4
27 zephyr,vref-mv = <3300>;
28 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
30 zephyr,input-positive = <MCUX_LPADC_CH0A>;
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/dac/dac_loopback/src/ |
| D | test_dac.c | 4 * SPDX-License-Identifier: Apache-2.0
37 * DAC output on PA4 (Arduino A2 pin of Nucleo board)
38 * ADC input read from PA1 (Arduino A1 pin of Nucleo board)
43 #define DAC_RESOLUTION 12
51 #define ADC_RESOLUTION 12
70 #define DAC_RESOLUTION 12
74 #define ADC_RESOLUTION 12
88 #define DAC_RESOLUTION 12
92 #define ADC_RESOLUTION 12
103 #define DAC_RESOLUTION 12
[all …]
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| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | pinctrl_eos_s3.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
29 #define PAD_SCHMITT_EN_BIT 12
34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
39 return -EINVAL; in pinctrl_eos_s3_input_selection()
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
55 return -EINVAL; in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
[all …]
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| D | Kconfig.stm32 | 2 # SPDX-License-Identifier: Apache-2.0
5 bool "Pin controller driver for STM32 MCUs"
9 Enable pin controller driver for STM32 MCUs
17 remap for pins PA11/12.
|
| /Zephyr-Core-3.5.0/samples/drivers/adc/boards/ |
| D | lpcxpresso55s69_cpu0.overlay | 2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2023 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
[all …]
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| D | mimxrt685_evk_cm33.overlay | 2 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
13 io-channels = <&lpadc0 0>, <&lpadc0 1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 * - Connect VREF_L to GND, and VREF_H to 1.8V (connect JP9 and JP10).
24 * - Connect LPADC0 CH0A signal to voltage between 0~1.8V (J30 pin 1)
25 * - Connect LPADC0 CH0B signal to voltage between 0~1.8V (J30 pin 2)
32 zephyr,vref-mv = <1800>;
33 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
[all …]
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| D | mchp-xec-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/dt-util.h>
23 #define MCHP_XEC_NO_PUD_POS 12
39 #define MCHP_XEC_DRV_STR0_1X 0x1 /* 2 or 4(PIO-24) mA */
40 #define MCHP_XEC_DRV_STR0_2X 0x2 /* 4 or 8(PIO-24) mA */
41 #define MCHP_XEC_DRV_STR0_4X 0x3 /* 8 or 16(PIO-24) mA */
42 #define MCHP_XEC_DRV_STR0_6X 0x4 /* 12 or 24(PIO-24) mA */
53 /* n is octal pin number or equivalent in another base.
54 * MCHP XEC documentation specifies pin numbers in octal.
56 * b[3:0] = pin bank
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | raspberrypi,pico-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
39 /* enable input on pin 1 */
40 input-enable;
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
22 #define MIO_PIN_PULLUP_MASK BIT(12)
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
120 #define MIO12 12
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
[all …]
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| /Zephyr-Core-3.5.0/samples/bluetooth/direction_finding_peripheral/boards/ |
| D | nrf52833dk_nrf52833.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 dfe-antenna-num = <12>;
13 /* This is a setting that enables antenna 12 (in antenna matrix designed
16 dfe-pdu-antenna = <0x0>;
18 /* These are GPIO pin numbers that are provided to
21 * Pin numbers are selected to drive switches on antenna matrix
24 dfegpio0-gpios = <&gpio0 3 0>;
25 dfegpio1-gpios = <&gpio0 4 0>;
26 dfegpio2-gpios = <&gpio0 28 0>;
27 dfegpio3-gpios = <&gpio0 29 0>;
|
| /Zephyr-Core-3.5.0/samples/bluetooth/direction_finding_central/boards/ |
| D | nrf52833dk_nrf52833.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 dfe-antenna-num = <12>;
13 /* This is a setting that enables antenna 12 (in antenna matrix designed
16 dfe-pdu-antenna = <0x0>;
18 /* These are GPIO pin numbers that are provided to
21 * Pin numbers are selected to drive switches on antenna matrix
24 dfegpio0-gpios = <&gpio0 3 0>;
25 dfegpio1-gpios = <&gpio0 4 0>;
26 dfegpio2-gpios = <&gpio0 28 0>;
27 dfegpio3-gpios = <&gpio0 29 0>;
|
| /Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/src/ |
| D | main_afio.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 14U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/boards/ |
| D | nucleo_f091rc.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
8 * i2c2 PA12 CN10:12 PA11 CN10:14
10 * Short Pin PB9 to PA12, and PB8 to PA11, for the test to pass.
15 compatible = "zephyr,i2c-target-eeprom";
23 /* i2c2 is disabled by default because of pin conflict with can1 */
26 compatible = "zephyr,i2c-target-eeprom";
|
| D | nucleo_g071rb.overlay | 3 * SPDX-License-Identifier: Apache-2.0
9 * Pin Hdr Pin Hdr
11 * i2c2 PA12 CN10:12 PA11 CN10:14
13 * Short Pin PB9 to PA12, and PB8 to PA11, for the test to pass.
18 compatible = "zephyr,i2c-target-eeprom";
26 compatible = "zephyr,i2c-target-eeprom";
|
| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
15 * @brief ITE IT8XXX2 pin type.
21 * Pin configuration
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
27 /* GPIO pin */
28 uint8_t pin; member
36 * @brief PIN configuration bitfield.
38 * Pin configuration is coded with the following
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/ |
| D | soc_i2c.h | 3 * SPDX-License-Identifier: Apache-2.0
14 /* 144-pin package I2C port masks */
33 #define MCHP_I2C_PORT_12 12
40 * Read pin states of specified I2C port.
42 * lines b[0]=SCL pin state at pad, b[1]=SDA pin state at pad
43 * Returns 0 success or -EINVAL if port is not support or lines is NULL.
|
