| /Zephyr-Core-3.5.0/soc/x86/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
34 #define APL_GPIO_11 11
49 #define APL_GPIO_26 26
68 #define APL_GPIO_43 11
83 #define APL_GPIO_70 26
102 #define APL_GPIO_SVID0_ALERT_B 11
118 #define APL_GPIO_198 11
133 #define APL_GPIO_213 26
152 #define APL_GPIO_83 11
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_ecia.h | 4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_LAST_GIRQ_NOS 26u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
27 BIT(26))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
60 * Each GIRQ is composed of 5 32-bit registers.
[all …]
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| /Zephyr-Core-3.5.0/samples/sensor/isl29035/boards/ |
| D | nrf52dk_nrf52832.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ALERT P1.11 */
11 int-gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
| /Zephyr-Core-3.5.0/samples/sensor/adt7420/boards/ |
| D | nrf52dk_nrf52832.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 &i2c0 { /* SDA P0.26, SCL P0.27, ALERT P0.11 */
9 clock-frequency = <I2C_BITRATE_STANDARD>;
13 int-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
|
| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/ |
| D | soc_pins.h | 4 * SPDX-License-Identifier: Apache-2.0
26 #define MCHP_GPIO_013 (11U)
41 #define MCHP_GPIO_032 (26U)
60 #define MCHP_GPIO_053 (11U)
75 #define MCHP_GPIO_072 (26U)
94 #define MCHP_GPIO_113 (11U)
109 #define MCHP_GPIO_132 (26U)
128 #define MCHP_GPIO_153 (11U)
143 #define MCHP_GPIO_172 (26U)
162 #define MCHP_GPIO_213 (11U)
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | rpi-pico-rp2040-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
42 #define UART1_RTS_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART)
57 #define UART1_CTS_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART)
73 #define I2C1_SCL_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C)
88 #define I2C1_SDA_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C)
104 #define PWM_5B_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM)
119 #define PWM_5A_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM)
135 #define SPI1_TX_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI)
150 #define SPI1_SCK_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI)
155 #define ADC_CH0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL)
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/cc26x2r1_launchxl/ |
| D | boosterpack_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "ti,boosterpack-header";
10 #gpio-cells = <2>;
11 gpio-map = <2 0 &gpio0 23 0>,
20 <11 0 &gpio0 15 0>,
25 <18 0 &gpio0 11 0>,
28 <24 0 &gpio0 26 0>,
30 <26 0 &gpio0 28 0>,
|
| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | raspberrypi,pico-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 This binding provides a nexus mapping for the default 26 pins as depicted below:
11 0 GPIO0/UART0_TX VBUS -
12 1 GPIO1/UART0_RX VSYS -
13 - GND GND -
14 2 GPIO2 3V3_EN -
15 3 GPIO3 3V3_OUT -
16 4 GPIO4/I2C0_SDA ADC_VREF -
18 - GND GND -
20 7 GPIO7 GPIO26/ADC0 26
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #define MIO_PIN_IO_TYPE_MASK GENMASK(11, 9)
119 #define MIO11 11
134 #define MIO26 26
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
190 #define MIO_GROUP_SPI1_1_SS1_PINS 26
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/pinnacle_100_dvk/ |
| D | pinnacle_100_dvk-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
22 low-power-enable;
41 low-power-enable;
47 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
56 low-power-enable;
63 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
71 <NRF_PSEL(SPIM_MOSI, 0, 26)>,
73 low-power-enable;
79 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/circuitdojo_feather_nrf9160/ |
| D | circuitdojo_feather_nrf9160_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
61 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 low-power-enable;
76 low-power-enable;
82 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
90 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/actinius_icarus/ |
| D | actinius_icarus_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
39 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
46 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
48 low-power-enable;
65 low-power-enable;
72 <NRF_PSEL(PWM_OUT1, 0, 11)>,
81 <NRF_PSEL(PWM_OUT1, 0, 11)>,
83 low-power-enable;
|
| /Zephyr-Core-3.5.0/dts/x86/intel/ |
| D | apollo_lake.dtsi | 2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/gpio/ |
| D | microchip-xec-gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
39 #define MCHP_GPIO_DECODE_013 XEC_GPIO_HELPER(&gpio_000_036, 11)
54 #define MCHP_GPIO_DECODE_032 XEC_GPIO_HELPER(&gpio_000_036, 26)
72 #define MCHP_GPIO_DECODE_053 XEC_GPIO_HELPER(&gpio_040_076, 11)
87 #define MCHP_GPIO_DECODE_072 XEC_GPIO_HELPER(&gpio_040_076, 26)
105 #define MCHP_GPIO_DECODE_113 XEC_GPIO_HELPER(&gpio_100_136, 11)
120 #define MCHP_GPIO_DECODE_132 XEC_GPIO_HELPER(&gpio_100_136, 26)
138 #define MCHP_GPIO_DECODE_153 XEC_GPIO_HELPER(&gpio_140_176, 11)
153 #define MCHP_GPIO_DECODE_172 XEC_GPIO_HELPER(&gpio_140_176, 26)
171 #define MCHP_GPIO_DECODE_213 XEC_GPIO_HELPER(&gpio_200_236, 11)
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/sparkfun_thing_plus_nrf9160/ |
| D | sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
54 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
61 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
63 low-power-enable;
77 low-power-enable;
83 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
91 psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/reel_board/dts/ |
| D | reel_board-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
14 bias-pull-up;
22 low-power-enable;
37 low-power-enable;
43 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
50 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
52 low-power-enable;
61 psels = <NRF_PSEL(PWM_OUT1, 0, 11)>,
71 <NRF_PSEL(PWM_OUT1, 0, 11)>,
74 low-power-enable;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/nrf9161dk_nrf9161/ |
| D | nrf9161dk_nrf9161_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
13 psels = <NRF_PSEL(UART_RX, 0, 26)>,
15 bias-pull-up;
22 <NRF_PSEL(UART_RX, 0, 26)>,
25 low-power-enable;
37 bias-pull-up;
47 low-power-enable;
62 low-power-enable;
75 low-power-enable;
83 <NRF_PSEL(SPIM_MOSI, 0, 11)>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/microchip/ |
| D | mec172xnsz.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf9160/ |
| D | nrf9160dk_nrf9160_common-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
14 <NRF_PSEL(UART_CTS, 0, 26)>;
15 bias-pull-up;
24 <NRF_PSEL(UART_CTS, 0, 26)>;
25 low-power-enable;
37 bias-pull-up;
47 low-power-enable;
62 low-power-enable;
77 low-power-enable;
90 low-power-enable;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/ubx_evkannab1_nrf52832/ |
| D | ubx_evkannab1_nrf52832-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
11 <NRF_PSEL(UART_RTS, 0, 11)>,
20 <NRF_PSEL(UART_RTS, 0, 11)>,
22 low-power-enable;
37 low-power-enable;
52 low-power-enable;
60 <NRF_PSEL(PWM_OUT2, 0, 26)>;
69 <NRF_PSEL(PWM_OUT2, 0, 26)>;
70 low-power-enable;
87 low-power-enable;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/rak4631_nrf52840/ |
| D | rak4631_nrf52840-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
63 low-power-enable;
69 psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
77 psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
80 low-power-enable;
91 <NRF_PSEL(QSPI_CSN, 0, 26)>;
102 <NRF_PSEL(QSPI_CSN, 0, 26)>;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s36/ |
| D | lpcxpresso55s36.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "lpcxpresso55s36-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 zephyr,code-partition = &sramx;
22 zephyr,shell-uart = &flexcomm0;
24 zephyr,flash-controller = &iap;
33 usart-0 = &flexcomm0;
34 pwm-0 = &flexpwm1_pwm0;
38 compatible = "gpio-leds";
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/cc1352r1_launchxl/ |
| D | boosterpack_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "ti,boosterpack-header";
10 #gpio-cells = <2>;
11 gpio-map = <2 0 &gpio0 23 0>,
24 <18 0 &gpio0 11 0>,
27 <24 0 &gpio0 26 0>,
29 <26 0 &gpio0 28 0>,
|
| /Zephyr-Core-3.5.0/include/zephyr/math/ |
| D | ilog2.h | 4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
62 (((n) & BIT(11)) == BIT(11)) ? 11 : \
97 find_msb_set(n) - 1 \
|
| /Zephyr-Core-3.5.0/dts/bindings/ieee802154/ |
| D | atmel,rf2xx.yaml | 1 # Copyright (c) 2019-2020 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
8 include: spi-device.yaml
11 irq-gpios:
12 type: phandle-array
15 reset-gpios:
16 type: phandle-array
19 slptr-gpios:
20 type: phandle-array
23 Multi-functional pin that controls sleep, deep sleep, transmit
[all …]
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