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/Zephyr-Core-3.5.0/boards/arm/mm_feather/
Dmmfeather_sdram_ini_dcd.c20 0xD2,
22 0x04, 0x30,
24 0x41,
26 0xCC, 0x03, 0xAC, 0x04,
28 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
30 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
32 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
34 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
36 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
38 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
[all …]
/Zephyr-Core-3.5.0/boards/arm/mm_swiftio/
Dmmswiftio_sdram_ini_dcd.c20 0xD2,
22 0x04, 0x30,
24 0x41,
26 0xCC, 0x03, 0xAC, 0x04,
28 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
30 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
32 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
34 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
36 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
38 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
[all …]
/Zephyr-Core-3.5.0/arch/sparc/core/
Dstack_offsets.h16 #define STACK_FRAME_L0_OFFSET 0x00
17 #define STACK_FRAME_L1_OFFSET 0x04
18 #define STACK_FRAME_L2_OFFSET 0x08
19 #define STACK_FRAME_L3_OFFSET 0x0c
20 #define STACK_FRAME_L4_OFFSET 0x10
21 #define STACK_FRAME_L5_OFFSET 0x14
22 #define STACK_FRAME_L6_OFFSET 0x18
23 #define STACK_FRAME_L7_OFFSET 0x1c
24 #define STACK_FRAME_I0_OFFSET 0x20
25 #define STACK_FRAME_I1_OFFSET 0x24
[all …]
Dwindow_trap.S25 std %l0, [%sp + 0x00]
26 std %l2, [%sp + 0x08]
27 std %l4, [%sp + 0x10]
29 std %l6, [%sp + 0x18]
33 std %i0, [%sp + 0x20]
36 std %i2, [%sp + 0x28]
40 std %i4, [%sp + 0x30]
42 std %i6, [%sp + 0x38]
65 ldd [%sp + 0x00], %l0
66 ldd [%sp + 0x08], %l2
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_xlnx_ps_bank.h18 + ((uint32_t)dev_conf->bank_index * 0x8))
19 #define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\
20 + ((uint32_t)dev_conf->bank_index * 0x8))
21 #define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\
22 + ((uint32_t)dev_conf->bank_index * 0x4))
23 #define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\
24 + ((uint32_t)dev_conf->bank_index * 0x4))
25 #define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\
26 + ((uint32_t)dev_conf->bank_index * 0x40))
27 #define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\
[all …]
/Zephyr-Core-3.5.0/tests/subsys/dsp/basicmath/src/
Dq7.pat2 0x52, 0x01, 0x47, 0x20, 0xA5, 0xFD, 0xFC, 0x44,
3 0xF5, 0xCB, 0x2A, 0xE7, 0x1E, 0x28, 0xFF, 0xEF,
4 0x3E, 0x2C, 0x05, 0x32, 0xAE, 0x09, 0xBE, 0xF5,
5 0x24, 0xFA, 0xDE, 0xD6, 0xF4, 0xE7, 0x0D, 0xD7,
6 0x10, 0x19, 0x0C, 0xC8, 0xBB, 0x1E, 0x05, 0xAA,
7 0x44, 0x60, 0x2D, 0x21, 0x1C, 0xF0, 0x2E, 0x25,
8 0xF4, 0xF1, 0xC7, 0x19, 0x26, 0xBB, 0xD0, 0x08,
9 0x46, 0xF9, 0xEF, 0x7E, 0x19, 0x1E, 0x1B, 0x0A,
10 0x1F, 0x22, 0x12, 0x10, 0x13, 0x05, 0x41, 0x0F,
11 0x3B, 0xF6, 0xF9, 0x45, 0xE5, 0xE4, 0x14, 0xCD,
[all …]
/Zephyr-Core-3.5.0/dts/arm/infineon/psoc6/psoc6_01/
Dpsoc6_01.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40250000 0x10000 >;
35 reg = <0x10000000 0x100000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x48000>;
55 reg = <0x40310000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40310000 0x4000>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/infineon/psoc6/psoc6_02/
Dpsoc6_02.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x200000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x100000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/icm42605/
Dicm42605_reg.h10 /* BANK 0 */
11 #define REG_DEVICE_CONFIG 0x11
12 #define REG_DRIVE_CONFIG 0x13
13 #define REG_INT_CONFIG 0x14
14 #define REG_FIFO_CONFIG 0x16
15 #define REG_TEMP_DATA1 0x1D
16 #define REG_TEMP_DATA0 0x1E
17 #define REG_ACCEL_DATA_X1 0x1F
18 #define REG_ACCEL_DATA_X0 0x20
19 #define REG_ACCEL_DATA_Y1 0x21
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/
Dm48x.dtsi14 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
27 flash0: flash@0 {
36 #clock-cells = <0>;
42 reg = <0x40000030 0x40
43 0x40000080 0x20>;
50 reg = <0x40004000 0x40>;
60 reg = <0x40004040 0x40>;
70 reg = <0x40004080 0x40>;
[all …]
Dm46x.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
32 reg = <0x20000000 DT_SIZE_K(512)>;
38 #clock-cells = <0>;
44 reg = <0x40000200 0x100>;
45 #clock-cells = <0>;
60 reg = <0x40000000 0x20>;
67 reg = <0x4000c000 0x110>;
71 flash0: flash@0 {
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/bmi08x/
Dbmi08x_config_file.h13 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x48, 0xb4, 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x6d,
14 0xb4, 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0xd4, 0xb3, 0x80, 0x2e, 0xb0, 0xb3, 0x80, 0x2e,
15 0x12, 0xb4, 0x50, 0x39, 0x21, 0x2e, 0xb0, 0xf0, 0x10, 0x30, 0x21, 0x2e, 0x16, 0xf0, 0x80,
16 0x2e, 0xfe, 0xb4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45,
18 0x79, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e,
19 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80,
20 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00,
21 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18,
22 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e, 0x18, 0x00, 0x80, 0x2e,
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/bmi270/
Dbmi270_config_file.h12 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x1a, 0x00, 0xc8, 0x2e, 0x00,
13 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e,
14 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0xc8, 0x2e, 0x00, 0x2e, 0x90,
15 0x32, 0x21, 0x2e, 0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x6a, 0xf5,
16 0x1a, 0x24, 0x22, 0x00, 0x80, 0x2e, 0x3b, 0x00, 0xc8, 0x2e, 0x44,
17 0x47, 0x22, 0x00, 0x37, 0x00, 0xa4, 0x00, 0xff, 0x0f, 0xd1, 0x00,
18 0x07, 0xad, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80,
19 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1,
20 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00,
21 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e,
[all …]
/Zephyr-Core-3.5.0/dts/riscv/openisa/
Drv32m1.dtsi22 #size-cells = <0>;
23 cpu@0 {
27 reg = <0>;
40 reg = <0x20000000 0x30000>;
45 reg = <0x09000000 0x20000>;
62 reg = <0x4002b000 0x200>;
68 reg = <0x41027000 0x200>;
74 #address-cells = <0>;
77 reg = <0xe0041000 0x88>;
82 #address-cells = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/atmel/
Dsaml2x.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0>;
37 reg = <0x20000000 0x8000>;
42 reg = <0x0080A00C 0x4>,
43 <0x0080A040 0x4>,
44 <0x0080A044 0x4>,
45 <0x0080A048 0x4>;
51 reg = <0x41004000 0x22>;
52 interrupts = <4 0>;
[all …]
Dsamd2x.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0>;
40 reg = <0x0080A00C 0x4>,
41 <0x0080A040 0x4>,
42 <0x0080A044 0x4>,
43 <0x0080A048 0x4>;
49 adc-0 = &adc;
51 sercom-0 = &sercom0;
64 reg = <0x41004000 0x22>;
[all …]
/Zephyr-Core-3.5.0/dts/riscv/telink/
Dtelink_b91.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
23 reg = <0>;
29 #address-cells = <0>;
42 ram_ilm: memory@0 {
52 reg = <0xe6000000 0x10000>;
53 interrupts = <7 0>;
59 reg = <0x80140100 0x40>;
72 reg = <0x80140180 0x40>;
83 reg = <0x80140300 0x08>;
[all …]
/Zephyr-Core-3.5.0/samples/modules/tflite-micro/tflm_ethosu/src/models/keyword_spotting_cnn_small_int8/
Dmodel.h12 0x1c, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x00, 0x00, 0x12, 0x00, 0x1c, 0x00, 0x18,
13 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x12, 0x00,
14 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 0x74, 0x2b, 0x01, 0x00, 0x08,
15 0x29, 0x01, 0x00, 0x80, 0x2b, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
16 0x38, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0xff, 0x05, 0x00, 0x00,
17 0x00, 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x4f, 0x66, 0x66, 0x6c, 0x69, 0x6e,
18 0x65, 0x4d, 0x65, 0x6d, 0x6f, 0x72, 0x79, 0x41, 0x6c, 0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69,
19 0x6f, 0x6e, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00,
20 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x6d, 0x69, 0x6e,
21 0x5f, 0x72, 0x75, 0x6e, 0x74, 0x69, 0x6d, 0x65, 0x5f, 0x76, 0x65, 0x72, 0x73, 0x69, 0x6f,
[all …]
/Zephyr-Core-3.5.0/drivers/display/
Dssd1306_regs.h12 #define SSD1306_CONTROL_ALL_BYTES_CMD 0x00
14 #define SSD1306_CONTROL_ALL_BYTES_DATA 0x40
16 #define SSD1306_CONTROL_BYTE_CMD 0x80
18 #define SSD1306_CONTROL_BYTE_DATA 0xc0
19 #define SSD1306_READ_STATUS_MASK 0xc0
20 #define SSD1306_READ_STATUS_BUSY 0x80
21 #define SSD1306_READ_STATUS_ON 0x40
26 #define SSD1306_SET_CONTRAST_CTRL 0x81 /* double byte command */
28 #define SSD1306_SET_ENTIRE_DISPLAY_OFF 0xa4
29 #define SSD1306_SET_ENTIRE_DISPLAY_ON 0xa5
[all …]
Ddisplay_st7789v.h11 #define ST7789V_CMD_NOP 0x00
12 #define ST7789V_CMD_SW_RESET 0x01
14 #define ST7789V_CMD_SLEEP_IN 0x10
15 #define ST7789V_CMD_SLEEP_OUT 0x11
16 #define ST7789V_CMD_INV_OFF 0x20
17 #define ST7789V_CMD_INV_ON 0x21
18 #define ST7789V_CMD_GAMSET 0x26
19 #define ST7789V_CMD_DISP_OFF 0x28
20 #define ST7789V_CMD_DISP_ON 0x29
22 #define ST7789V_CMD_CASET 0x2a
[all …]
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dfir_q7.pat2 0x00, 0x02, 0x04, 0x03, 0x02, 0xFE, 0xFD, 0xFC,
3 0xFD, 0x00, 0x02, 0x04, 0x03, 0x02, 0xFF, 0xFD,
4 0xFD, 0xFE, 0x00, 0x03, 0x04, 0x04, 0x01, 0xFF,
5 0xFC, 0xFC, 0xFD, 0x01, 0x03, 0x04, 0x03, 0x01,
6 0xFF, 0xFC, 0xFC, 0xFD, 0x00, 0x02, 0x04, 0x03,
7 0x02, 0xFF, 0xFD, 0xFC, 0xFE, 0x00
11 0x2B, 0x40, 0x20, 0x4D, 0x33, 0x1A, 0x55, 0x40,
12 0x2B, 0x15, 0x5B, 0x49, 0x37, 0x25, 0x12, 0x60,
13 0x50, 0x40, 0x30, 0x20, 0x10, 0x64, 0x55, 0x47,
14 0x39, 0x2B, 0x1C, 0x0E, 0x66, 0x5A, 0x4D, 0x40,
[all …]
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_s32z27x_r52.dtsi14 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
85 reg = <0x40030000 0x10000>,
86 <0x40200000 0x10000>,
87 <0x40210000 0x10000>,
88 <0x40220000 0x10000>,
89 <0x40260000 0x10000>,
90 <0x40270000 0x10000>,
91 <0x40830000 0x10000>,
[all …]
Dnxp_kl25z.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
29 reg = <0x1FFFF000 DT_SIZE_K(16)>;
41 reg = <0x40020000 0x14>;
42 interrupts = <5 0>;
48 flash0: flash@0 {
50 reg = <0 DT_SIZE_K(128)>;
58 reg = <0x40064000 0xd>;
66 #size-cells = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/display/
Dilitek,ili9488.yaml13 default: [0xb0, 0x11]
19 default: [0x02, 0x02, 0x3b]
22 default SS bit value (0) may interfere with display rotation.
26 default: [0x0e, 0x0e]
32 default: [0x43]
38 default: [0x00, 0x40, 0x00, 0x40]
45 0x0f,
46 0x1f,
47 0x1c,
48 0x0b,
[all …]
/Zephyr-Core-3.5.0/tests/net/icmpv6/src/
Dmain.c41 "\x60\x02\xea\x12\x00\x40\x3a\x40\xfe\x80\x00\x00\x00\x00\x00\x00" \
50 "\x60\x09\x23\xa0\x00\x40\x3a\x40\xfe\x80\x00\x00\x00\x00\x00\x00" \
59 "\x60\x09\x23\xa0\x00\x40\x3a\x40\xfe\x80\x00\x00\x00\x00\x00\x00" \
80 return 0; in net_icmpv6_dev_init()
87 if (context->mac_addr[2] == 0x00) { in net_icmpv6_get_mac()
89 context->mac_addr[0] = 0x00; in net_icmpv6_get_mac()
90 context->mac_addr[1] = 0x00; in net_icmpv6_get_mac()
91 context->mac_addr[2] = 0x5E; in net_icmpv6_get_mac()
92 context->mac_addr[3] = 0x00; in net_icmpv6_get_mac()
93 context->mac_addr[4] = 0x53; in net_icmpv6_get_mac()
[all …]

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