Home
last modified time | relevance | path

Searched +full:- +full:- +full:add +full:- +full:architecture (Results 1 – 25 of 145) sorted by relevance

123456

/Zephyr-latest/drivers/ethernet/
DKconfig.dsa1 # Distributed Switch Architecture [DSA] configuration options
5 # SPDX-License-Identifier: Apache-2.0
13 bool "Distributed Switch Architecture support"
16 Enable Distributed Switch Architecture support. For now it
31 Add support for KSZ8794 DSA device driver.
40 Add support for KSZ8863 DSA device driver.
46 Add support for tail tagging on DSA device.
55 module-dep = NET_LOG
56 module-str = Log level for DSA
57 module-help = Enables core DSA code to output debug messages.
/Zephyr-latest/doc/services/dsp/
Dindex.rst10 The DSP API provides an architecture agnostic way for signal processing.
11 Currently, the API will work on any architecture but will likely not be
15 Architecture Status
44 Optimizing for your architecture
47 If your architecture is showing as ``Unoptimized``, it's possible to add a new
53 linked in at :file:`subsys/dsp/CMakeLists.txt`. To add architecture-specific attributes,
62 .. _subsys/dsp/Kconfig: https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/dsp/Kconfig
63 .. _subsys/dsp/CMakeLists.txt: https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/dsp/CM…
64 .. _include/zephyr/dsp/dsp.h: https://github.com/zephyrproject-rtos/zephyr/blob/main/include/zephyr…
/Zephyr-latest/subsys/testsuite/ztest/unittest/include/zephyr/arch/
Dcpu.h2 * SPDX-License-Identifier: Apache-2.0
15 /* Architecture thread structure */
18 /* C++ does not allow empty structs, add an extra 1 byte */
27 /* C++ does not allow empty structs, add an extra 1 byte */
34 /* Architecture functions */
/Zephyr-latest/include/zephyr/arch/arm/
Dstructs.h3 * SPDX-License-Identifier: Apache-2.0
12 /* Per CPU architecture specifics */
19 /* Default definitions when no architecture specific definitions exist. */
21 /* Per CPU architecture specifics (empty) */
25 * prevent this, we add a 1 byte dummy variable.
/Zephyr-latest/include/zephyr/arch/
Dstructs.h4 * SPDX-License-Identifier: Apache-2.0
8 * The purpose of this file is to provide essential/minimal architecture-
34 /* Default definitions when no architecture specific definitions exist. */
36 /* Per CPU architecture specifics (empty) */
40 * prevent this, we add a 1 byte dummy variable.
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
61 * specified as part of the architecture API, in practice virtually
82 * through the full 64 bit space, wrapping at 2^64-1. Hardware with
92 * @addtogroup arch-threads
[all …]
/Zephyr-latest/boards/
Dindex.rst6 If you are looking to add Zephyr support for a new board, please start with the
12 Shields are hardware add-ons that can be stacked on top of a board to add extra
14 this page <boards-shields>`.
23 both a vendor and an architecture, only boards that match both will be displayed. Within a
28 MCU exists, you can use it as a :ref:`starting point <create-your-board-directory>` for adding
38 .. zephyr:board-catalog::
40 .. _boards-shields:
/Zephyr-latest/boards/cdns/xt-sim/doc/
Dindex.rst1 .. zephyr:board:: xt-sim
6 The Xtensa processor architecture is a configurable, extensible, and
7 synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
11 For more information, see https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
18 - sample_controller
35 Only Xtensa tools version ``RF-2016.4-linux`` or later are officially
38 In order to set up the Zephyr OS build system, a Linux 32-bit GCC compiler must
42 On Debian/Ubuntu systems, you can install ``gcc-multilib`` package as follows:
44 .. code-block:: console
46 #aptitude install gcc-multilib # Or what ever package manager (apt, apt-get, ...)
[all …]
/Zephyr-latest/kernel/
DKconfig.smp2 # SPDX-License-Identifier: Apache-2.0
15 bool "Use new-style _arch_switch instead of arch_swap"
20 for an SMP-aware scheduler, or if the architecture does not
22 architecture provides both, _arch_switch incurs more somewhat
38 (architecture/SoC/board/application) to boot secondary CPUs at
46 Maximum number of multiprocessing-capable cores available to the
52 True if the architecture supports a call to arch_sched_broadcast_ipi()
74 When true, it will add a hook into z_sched_ipi(), in order
91 application behavior. If the architecture also supports directing
105 where all shared data is placed in multiprocessor-coherent
[all …]
/Zephyr-latest/doc/services/debugging/
Dcoredump.rst48 are enabled. This core dump data can be fed into a custom-made GDB server as
68 4. Start the debugger corresponding to the target architecture.
71 Developers for Intel ADSP CAVS 15-25 platforms using
73 ``xtensa-intel_apl_adsp`` toolchain of the SDK.
79 .. code-block:: devicetree
84 label = "coredump-partition";
90 -------
100 Booting from ROM..*** Booting Zephyr OS build zephyr-v2.3.0-1840-g7bba91944a63 ***
105 E: PTE: Non-present
166 .. code-block:: console
[all …]
/Zephyr-latest/arch/arm64/core/
Disr_wrapper.S4 * SPDX-License-Identifier: Apache-2.0
8 * ARM64 Cortex-A ISRs wrapper
35 /* ++_current_cpu->nested to be checked by arch_is_in_isr() */
38 add w2, w1, #1
46 str x2, [sp, #-16]!
70 * Architecture Specification GIC architecture version 3 and version 4
81 mov x1, #(CONFIG_NUM_IRQS - 1)
85 stp x0, xzr, [sp, #-16]!
89 add x1, x1, x0, lsl #4 /* table is 16-byte wide */
100 /* Signal end-of-interrupt */
[all …]
DKconfig4 # SPDX-License-Identifier: Apache-2.0
18 This option signifies the use of a CPU of the Cortex-A family.
31 This option signifies the use of a CPU of the Cortex-R 64-bit family.
38 This option signifies the use of a Cortex-A53 CPU
45 This option signifies the use of a Cortex-A55 CPU
52 This option signifies the use of a Cortex-A57 CPU
59 This option signifies the use of a Cortex-A72 CPU
66 This option signifies the use of a Cortex-A76 CPU
73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
80 This option signifies the use of a Cortex-R82 CPU
[all …]
/Zephyr-latest/doc/contribute/
Dcontributor_expectations.rst1 .. _contributor-expectations:
10 - Reviewed more quickly and reviewed more thoroughly. It's easier for reviewers
14 - Less wasted work if reviewers or maintainers reject the direction of the
17 - Easier to rebase and merge. Smaller PRs are less likely to conflict with other
20 - Easier to revert if the PR breaks functionality.
32 - Smaller PRs should encompass one self-contained logical change.
34 - When adding a new large feature or API, the PR should address only one part of
38 - PRs should include tests or samples under the following conditions:
40 - Adding new features or functionality.
42 - Modifying a feature, especially for API behavior contract changes.
[all …]
Dguidelines.rst6 As an open-source project, we welcome and encourage the community to submit
24 https://github.com/zephyrproject-rtos/zephyr/blob/main/LICENSE
26 .. _GitHub repo: https://github.com/zephyrproject-rtos/zephyr
38 https://www.zephyrproject.org/faqs/#1571346989065-9216c551-f523
41 https://www.whitesourcesoftware.com/whitesource-blog/top-10-apache-license-questions-answered/
64 See :ref:`external-contributions` for more information about
84 https://www.linuxfoundation.org/blog/copyright-notices-in-open-source-software-projects/
97 later in this document), the developer simply adds a ``Signed-off-by``
104 .. code-block:: none
129 sign-off) is maintained indefinitely and may be redistributed
[all …]
/Zephyr-latest/drivers/pcie/host/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
14 module-str = pcie
26 Add support for PCIe Controller management when not handled by a
34 Add support for Enhanced Configuration Address Mapping configured
43 Use Message-Signaled Interrupts where possible. With this option
51 bool "MSI multi-vector support"
55 assigned to it. This will require for the selected architecture
61 bool "MSI-X support"
63 If one or more device support MSI-X, you'll need to enable this.
64 If a device exposes support for both MSI-X and MSI, MSI-X will be
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-1.7.rst8 kernel release, simplifying the overall Zephyr architecture and programming
10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
22 STML32L476 based SoCs. Plan is to add support for other architectures and
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
56 * Added Qemu target for RISC V and a simulator target for the Xtensa architecture.
75 add new networking features which are described below.
102 * Created net-shell module for interacting with network sub-system.
136 * Imported Segger J-Link RTT library
145 * New local-content generation theme (read-the-docs)
[all …]
Drelease-notes-1.5.rst7 1.5.0. This is the first release to follow the 3-month release cadence.
13 - TCP Support
14 - Integration of the Paho MQTT Library support with QoS
15 - Flash Filesystem Support
16 - Integration of the mbedTLS library for encryption
17 - Improved BR/EDR support (for L2CAP, in particular).
18 - Support for the Altera Nios II/f soft CPU architecture
25 - Added nano_fifo_put_list() APIs, which allows queuing a list of elements
27 - Removed unused memory pool structure field.
28 - Enhanced memory pool code.
[all …]
/Zephyr-latest/arch/arm/core/cortex_m/
Dfault_s.S2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
3 * Copyright (c) 2017-2019 Nordic Semiconductor ASA.
5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Fault handlers for ARM Cortex-M
12 * Fault handlers for ARM Cortex-M processors.
24 /* HardFault is used for all fault conditions on ARMv6-M. */
34 #error Unknown ARM architecture
46 * - the MSP
47 * - the PSP
48 * - the EXC_RETURN value
[all …]
/Zephyr-latest/arch/arc/core/
Dreset.S4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/arch/arc/asm-compat/assembler.h>
122 * Init ARC internal architecture state
123 * Force to initialize internal architecture state to reset values
124 * For scenarios where board hardware is not re-initialized between tests,
169 * Non-masters wait for master core (core 0) to boot enough
199 add sp, sp, CONFIG_MAIN_STACK_SIZE
209 add sp, sp, INIT_STACK_SIZE
/Zephyr-latest/include/zephyr/arch/arm64/
Darch.h4 * SPDX-License-Identifier: Apache-2.0
12 * included by the kernel interface architecture-abstraction header
19 /* Add include for DTS generated information */
/Zephyr-latest/arch/arm64/core/cortex_r/
DKconfig6 # SPDX-License-Identifier: Apache-2.0
21 The ARMv8-R MPU architecture requires a power-of-two alignment
24 The ARMv8-R MPU requires the active MPU regions be non-overlapping.
25 As a result of this, the ARMv8-R MPU needs to fully partition the
29 of the ARMv8-R background memory map. The application developer may
33 SRAM area covered only by the default ARMv8-R memory map. This
41 of full partitioning the default behavior for the ARMv8-R MPU
51 A minimum 4-byte alignment is enforced in ARM builds without
57 bool "Add MPU access to write to flash"
/Zephyr-latest/doc/kernel/usermode/
Dmemory_domain.rst24 - Any configuration of memory regions which need to have special caching or
25 write-back policies for basic hardware and driver function. Note that most
30 ARMv7-M/ARMv8-M this is called the System Address Map, other CPUs may
34 - A read-only, executable region or regions for program text and ro-data, that
35 is accessible to user mode. This could be further sub-divided into a
36 read-only region for ro-data, and a read-only, executable region for text, but
38 threads running in user mode can read ro-data and fetch instructions.
40 - Depending on configuration, user-accessible read-write regions to support
45 text/ro-data, this is sufficient for the boot time configuration.
53 individual stack frames, use compiler-assisted :kconfig:option:`CONFIG_STACK_CANARIES`
[all …]
/Zephyr-latest/doc/hardware/porting/
Dsoc_porting.rst6 This page describes how to add support for a new :term:`SoC` in Zephyr, be it in
18 - SoC: the exact system on a chip the board's CPU is part of.
19 - SoC series: a group of tightly related SoCs.
20 - SoC family: a wider group of SoCs with similar characteristics.
21 - CPU Cluster: a cluster of one or more CPU cores.
22 - CPU core: a particular CPU instance of a given architecture.
23 - Architecture: an instruction set architecture.
25 Architecture subsection
39 in Zephyr, for example ``./scripts/list_hardware.py --soc-root=. --socs`` from
48 structure under ``<your-repo>/soc`` is permitted.
[all …]
/Zephyr-latest/doc/develop/api/
Dapi_lifecycle.rst16 :figclass: align-center
20 An up-to-date table of all APIs and their maturity level can be found in the
35 - Documentation of the API (usage)
38 - The API introduction should be accompanied by at least one implementation
40 - At least one sample using the new API (may only build on one single board)
51 the Architecture working group consisting of representatives from different vendors.
61 The API is in the process of settling, but has not yet had sufficient real-world
91 minor changes. Backwards-compatibility will be maintained if reasonable.
95 - Test cases for the new API with 100% coverage
96 - Complete documentation in code. All public interfaces shall be documented
[all …]
/Zephyr-latest/arch/
DKconfig1 # General architecture configuration options
3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
16 # Architecture symbols
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
29 ARC architecture
37 # is really only necessary for Cortex-M with ARM MPU!
42 ARM architecture
60 ARM64 (AArch64) architecture
67 MIPS architecture
[all …]

123456