1/* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 13#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 14 15/ { 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-m33f"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32 33 soc { 34 sram: sram@10000000 { 35 ranges = <0x0 0x10000000 0x780000 36 0x20000000 0x30000000 0x780000>; 37 }; 38 39 peripheral: peripheral@50000000 { 40 ranges = <0x0 0x50000000 0x10000000>; 41 }; 42 43 xspi0: spi@50184000 { 44 reg = <0x50184000 0x1000>, <0x38000000 DT_SIZE_M(128)>; 45 }; 46 47 xspi1: spi@50185000 { 48 reg = <0x50185000 0x1000>, <0x18000000 DT_SIZE_M(128)>; 49 }; 50 51 xspi2: spi@50411000 { 52 reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; 53 }; 54 55 }; 56 57 pinctrl: pinctrl { 58 compatible = "nxp,rt-iocon-pinctrl"; 59 }; 60 61 /* USB PLL */ 62 usbclk: usbpll-clock { 63 compatible = "fixed-clock"; 64 clock-frequency = <24000000>; 65 #clock-cells = <0>; 66 }; 67}; 68 69 70&sram { 71 #address-cells = <1>; 72 #size-cells = <1>; 73 74 /* RT7XX SRAM partitions are shared between code and data. Boards can override 75 * the reg properties of either sram0 or sram_code nodes to change the balance 76 * of SRAM allocation. 77 * 78 * The SRAM region [0x000000-0x017FFF] is reserved for ROM bootloader execution. 79 * Can be reused after boot. 80 * The SRAM region [0x018000-0x17FFFF] is reserved for Non-cached shared memory 81 * or application data. 82 * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last 83 * 2MB non-cacheable data for NPU/GPU/Display etc. 84 * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application. 85 */ 86 87 sram4rom: memory@20000000{ 88 compatible = "mmio-sram"; 89 reg = <0x20000000 DT_SIZE_K(96)>; 90 }; 91 92 /* This partition is shared with code in RAM */ 93 sram_shared_code: memory@20018000{ 94 compatible = "mmio-sram"; 95 reg = <0x20018000 DT_SIZE_K(1024+512-96)>; 96 }; 97 98 sram0: memory@20180000 { 99 compatible = "mmio-sram"; 100 reg = <0x20180000 DT_SIZE_K(512)>; 101 }; 102 103 sram1: memory@20200000 { 104 compatible = "mmio-sram"; 105 reg = <0x20200000 DT_SIZE_K(2048)>; 106 }; 107}; 108 109&peripheral { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 /* 113 * Note that the offsets here are relative to the base address. 114 * The base addresses differ between non-secure (0x40000000) 115 * and secure modes (0x50000000). 116 */ 117 118 lpadc0: adc@20c000 { 119 compatible = "nxp,lpc-lpadc"; 120 reg = <0x20c000 0x304>; 121 interrupts = <15 0>; 122 status = "disabled"; 123 clk-divider = <1>; 124 clk-source = <0>; 125 voltage-ref= <1>; 126 calibration-average = <128>; 127 power-level = <0>; 128 offset-value-a = <10>; 129 offset-value-b = <10>; 130 #io-channel-cells = <1>; 131 clocks = <&clkctl3 MCUX_LPADC1_CLK>; 132 }; 133 134 rstctl0: reset@0 { 135 compatible = "nxp,rstctl"; 136 reg = <0x0 0x1000>; 137 #reset-cells = <1>; 138 }; 139 140 rstctl2: reset@67000 { 141 compatible = "nxp,rstctl"; 142 reg = <0x67000 0x1000>; 143 #reset-cells = <1>; 144 }; 145 146 rstctl3: reset@60000 { 147 compatible = "nxp,rstctl"; 148 reg = <0x60000 0x1000>; 149 #reset-cells = <1>; 150 }; 151 152 rstctl4: reset@a0000 { 153 compatible = "nxp,rstctl"; 154 reg = <0xa0000 0x1000>; 155 #reset-cells = <1>; 156 }; 157 158 clkctl0: clkctl@1000 { 159 compatible = "nxp,lpc-syscon"; 160 reg = <0x1000 0x1000>; 161 #clock-cells = <1>; 162 }; 163 164 clkctl2: clkctl@65000 { 165 compatible = "nxp,lpc-syscon"; 166 reg = <0x65000 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 clkctl3: clkctl@61000 { 171 compatible = "nxp,lpc-syscon"; 172 reg = <0x61000 0x1000>; 173 #clock-cells = <1>; 174 }; 175 176 clkctl4: clkctl@a1000 { 177 compatible = "nxp,lpc-syscon"; 178 reg = <0xa1000 0x1000>; 179 #clock-cells = <1>; 180 }; 181 182 ctimer0: ctimer@28000 { 183 compatible = "nxp,lpc-ctimer"; 184 reg = <0x28000 0x1000>; 185 interrupts = <3 0>; 186 status = "disabled"; 187 clk-source = <1>; 188 clocks = <&clkctl0 MCUX_CTIMER0_CLK>; 189 mode = <0>; 190 input = <0>; 191 prescale = <0>; 192 }; 193 194 ctimer1: ctimer@29000 { 195 compatible = "nxp,lpc-ctimer"; 196 reg = <0x29000 0x1000>; 197 interrupts = <4 0>; 198 status = "disabled"; 199 clk-source = <1>; 200 clocks = <&clkctl0 MCUX_CTIMER1_CLK>; 201 mode = <0>; 202 input = <0>; 203 prescale = <0>; 204 }; 205 206 ctimer2: ctimer@2a000 { 207 compatible = "nxp,lpc-ctimer"; 208 reg = <0x2a000 0x1000>; 209 interrupts = <32 0>; 210 status = "disabled"; 211 clk-source = <1>; 212 clocks = <&clkctl0 MCUX_CTIMER2_CLK>; 213 mode = <0>; 214 input = <0>; 215 prescale = <0>; 216 }; 217 218 ctimer3: ctimer@2b000 { 219 compatible = "nxp,lpc-ctimer"; 220 reg = <0x2b000 0x1000>; 221 interrupts = <6 0>; 222 status = "disabled"; 223 clk-source = <1>; 224 clocks = <&clkctl0 MCUX_CTIMER3_CLK>; 225 mode = <0>; 226 input = <0>; 227 prescale = <0>; 228 }; 229 230 ctimer4: ctimer@2c000 { 231 compatible = "nxp,lpc-ctimer"; 232 reg = <0x2c000 0x1000>; 233 interrupts = <33 0>; 234 status = "disabled"; 235 clk-source = <1>; 236 clocks = <&clkctl0 MCUX_CTIMER4_CLK>; 237 mode = <0>; 238 input = <0>; 239 prescale = <0>; 240 }; 241 242 edma0: dma-controller@140000 { 243 #dma-cells = <2>; 244 compatible = "nxp,mcux-edma"; 245 nxp,version = <4>; 246 dma-channels = <16>; 247 dma-requests = <105>; 248 reg = <0x140000 0x1000>; 249 interrupts = <59 0>, <60 0>, <61 0>, <62 0>, 250 <63 0>, <64 0>, <65 0>, <66 0>, 251 <67 0>, <68 0>, <69 0>, <70 0>, 252 <71 0>, <72 0>, <73 0>, <74 0>; 253 no-error-irq; 254 status = "disabled"; 255 }; 256 257 edma1: dma-controller@160000 { 258 #dma-cells = <2>; 259 compatible = "nxp,mcux-edma"; 260 nxp,version = <4>; 261 dma-channels = <16>; 262 dma-requests = <105>; 263 reg = <0x160000 0x1000>; 264 interrupts = <75 0>, <76 0>, <77 0>, <78 0>, 265 <79 0>, <80 0>, <81 0>, <82 0>, 266 <83 0>, <84 0>, <85 0>, <86 0>, 267 <87 0>, <88 0>, <89 0>, <90 0>; 268 no-error-irq; 269 status = "disabled"; 270 }; 271 272 syscon0: syscon@2000 { 273 compatible = "nxp,lpc-syscon"; 274 reg = <0x2000 0x1000>; 275 #clock-cells = <1>; 276 }; 277 278 syscon2: syscon@66000 { 279 compatible = "nxp,lpc-syscon"; 280 reg = <0x66000 0x1000>; 281 #clock-cells = <1>; 282 }; 283 284 syscon3: syscon@62000 { 285 compatible = "nxp,lpc-syscon"; 286 reg = <0x62000 0x1000>; 287 #clock-cells = <1>; 288 }; 289 290 syscon4: syscon@a2000 { 291 compatible = "nxp,lpc-syscon"; 292 reg = <0xa2000 0x1000>; 293 #clock-cells = <1>; 294 }; 295 296 iocon: iocon@4000 { 297 compatible = "nxp,lpc-iocon"; 298 reg = <0x4000 0x1000>; 299 status = "okay"; 300 }; 301 302 iocon1: iocon@64000 { 303 compatible = "nxp,lpc-iocon"; 304 reg = <0x64000 0x1000>; 305 status = "okay"; 306 }; 307 308 iocon2: iocon@a5000 { 309 compatible = "nxp,lpc-iocon"; 310 reg = <0xa5000 0x1000>; 311 status = "okay"; 312 }; 313 314 gpio0: gpio@100000 { 315 compatible = "nxp,kinetis-gpio"; 316 status = "disabled"; 317 reg = <0x100000 0x1000>; 318 interrupts = <91 0>,<92 0>; 319 gpio-controller; 320 #gpio-cells = <2>; 321 nxp,kinetis-port = <&gpio0>; 322 }; 323 324 gpio1: gpio@102000 { 325 compatible = "nxp,kinetis-gpio"; 326 status = "disabled"; 327 reg = <0x102000 0x1000>; 328 interrupts = <93 0>,<94 0>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 nxp,kinetis-port = <&gpio1>; 332 }; 333 334 gpio2: gpio@104000 { 335 compatible = "nxp,kinetis-gpio"; 336 status = "disabled"; 337 reg = <0x104000 0x1000>; 338 interrupts = <95 0>,<96 0>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 nxp,kinetis-port = <&gpio2>; 342 }; 343 344 gpio3: gpio@106000 { 345 compatible = "nxp,kinetis-gpio"; 346 status = "disabled"; 347 reg = <0x106000 0x1000>; 348 interrupts = <97 0>,<98 0>; 349 gpio-controller; 350 #gpio-cells = <2>; 351 nxp,kinetis-port = <&gpio3>; 352 }; 353 354 gpio4: gpio@108000 { 355 compatible = "nxp,kinetis-gpio"; 356 status = "disabled"; 357 reg = <0x108000 0x1000>; 358 interrupts = <99 0>,<100 0>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 nxp,kinetis-port = <&gpio4>; 362 }; 363 364 gpio5: gpio@10a000 { 365 compatible = "nxp,kinetis-gpio"; 366 status = "disabled"; 367 reg = <0x10a000 0x1000>; 368 interrupts = <101 0>,<102 0>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 nxp,kinetis-port = <&gpio5>; 372 }; 373 374 gpio6: gpio@10c000 { 375 compatible = "nxp,kinetis-gpio"; 376 status = "disabled"; 377 reg = <0x10c000 0x1000>; 378 interrupts = <103 0>,<104 0>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 nxp,kinetis-port = <&gpio6>; 382 }; 383 384 gpio7: gpio@10e000 { 385 compatible = "nxp,kinetis-gpio"; 386 status = "disabled"; 387 reg = <0x10e000 0x1000>; 388 interrupts = <105 0>,<106 0>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 nxp,kinetis-port = <&gpio7>; 392 }; 393 394 flexcomm0: flexcomm@110000 { 395 compatible = "nxp,lp-flexcomm"; 396 reg = <0x110000 0x1000>; 397 interrupts = <7 0>; 398 status = "disabled"; 399 400 /* Empty ranges property implies parent and child address space is identical */ 401 ranges = <>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 405 flexcomm0_lpuart0: uart@110000 { 406 compatible = "nxp,lpuart"; 407 reg = <0x110000 0x1000>; 408 clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; 409 status = "disabled"; 410 }; 411 412 flexcomm0_lpspi0: spi@110000 { 413 compatible = "nxp,lpspi"; 414 reg = <0x110000 0x1000>; 415 clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 tx-fifo-size = <8>; 419 rx-fifo-size = <8>; 420 status = "disabled"; 421 }; 422 423 flexcomm0_lpi2c0: lpi2c@110800 { 424 compatible = "nxp,lpi2c"; 425 reg = <0x110800 0x1000>; 426 clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 }; 432 433 flexcomm1: flexcomm@111000 { 434 compatible = "nxp,lp-flexcomm"; 435 reg = <0x111000 0x1000>; 436 interrupts = <8 0>; 437 status = "disabled"; 438 439 /* Empty ranges property implies parent and child address space is identical */ 440 ranges = <>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 444 flexcomm1_lpuart1: uart@111000 { 445 compatible = "nxp,lpuart"; 446 reg = <0x111000 0x1000>; 447 clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; 448 status = "disabled"; 449 }; 450 451 flexcomm1_lpspi1: spi@111000 { 452 compatible = "nxp,lpspi"; 453 reg = <0x111000 0x1000>; 454 clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 tx-fifo-size = <8>; 458 rx-fifo-size = <8>; 459 status = "disabled"; 460 }; 461 462 flexcomm1_lpi2c1: lpi2c@111800 { 463 compatible = "nxp,lpi2c"; 464 reg = <0x111800 0x1000>; 465 clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 status = "disabled"; 469 }; 470 }; 471 472 flexcomm2: flexcomm@112000 { 473 compatible = "nxp,lp-flexcomm"; 474 reg = <0x112000 0x1000>; 475 interrupts = <9 0>; 476 status = "disabled"; 477 478 /* Empty ranges property implies parent and child address space is identical */ 479 ranges = <>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 483 flexcomm2_lpuart2: uart@112000 { 484 compatible = "nxp,lpuart"; 485 reg = <0x112000 0x1000>; 486 clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; 487 status = "disabled"; 488 }; 489 490 flexcomm2_lpspi2: spi@112000 { 491 compatible = "nxp,lpspi"; 492 reg = <0x112000 0x1000>; 493 clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 tx-fifo-size = <8>; 497 rx-fifo-size = <8>; 498 status = "disabled"; 499 }; 500 501 flexcomm2_lpi2c2: lpi2c@112800 { 502 compatible = "nxp,lpi2c"; 503 reg = <0x112800 0x1000>; 504 clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 }; 510 511 flexcomm3: flexcomm@113000 { 512 compatible = "nxp,lp-flexcomm"; 513 reg = <0x113000 0x1000>; 514 interrupts = <10 0>; 515 status = "disabled"; 516 517 /* Empty ranges property implies parent and child address space is identical */ 518 ranges = <>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 522 flexcomm3_lpuart3: uart@113000 { 523 compatible = "nxp,lpuart"; 524 reg = <0x113000 0x1000>; 525 clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; 526 status = "disabled"; 527 }; 528 529 flexcomm3_lpspi3: spi@113000 { 530 compatible = "nxp,lpspi"; 531 reg = <0x113000 0x1000>; 532 clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 tx-fifo-size = <8>; 536 rx-fifo-size = <8>; 537 status = "disabled"; 538 }; 539 540 flexcomm3_lpi2c3: lpi2c@113800 { 541 compatible = "nxp,lpi2c"; 542 reg = <0x113800 0x1000>; 543 clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 status = "disabled"; 547 }; 548 }; 549 550 flexcomm4: flexcomm@171000 { 551 compatible = "nxp,lp-flexcomm"; 552 reg = <0x171000 0x1000>; 553 interrupts = <11 0>; 554 status = "disabled"; 555 556 /* Empty ranges property implies parent and child address space is identical */ 557 ranges = <>; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 561 flexcomm4_lpuart4: uart@171000 { 562 compatible = "nxp,lpuart"; 563 reg = <0x171000 0x1000>; 564 clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; 565 status = "disabled"; 566 }; 567 568 flexcomm4_lpspi4: spi@171000 { 569 compatible = "nxp,lpspi"; 570 reg = <0x171000 0x1000>; 571 clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 tx-fifo-size = <8>; 575 rx-fifo-size = <8>; 576 status = "disabled"; 577 }; 578 579 flexcomm4_lpi2c4: lpi2c@171800 { 580 compatible = "nxp,lpi2c"; 581 reg = <0x171800 0x1000>; 582 clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 }; 588 589 flexcomm5: flexcomm@172000 { 590 compatible = "nxp,lp-flexcomm"; 591 reg = <0x172000 0x1000>; 592 interrupts = <12 0>; 593 status = "disabled"; 594 595 /* Empty ranges property implies parent and child address space is identical */ 596 ranges = <>; 597 #address-cells = <1>; 598 #size-cells = <1>; 599 600 flexcomm5_lpuart5: uart@172000 { 601 compatible = "nxp,lpuart"; 602 reg = <0x172000 0x1000>; 603 clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; 604 status = "disabled"; 605 }; 606 607 flexcomm5_lpspi5: spi@172000 { 608 compatible = "nxp,lpspi"; 609 reg = <0x172000 0x1000>; 610 clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 tx-fifo-size = <8>; 614 rx-fifo-size = <8>; 615 status = "disabled"; 616 }; 617 618 flexcomm5_lpi2c5: lpi2c@172800 { 619 compatible = "nxp,lpi2c"; 620 reg = <0x172800 0x1000>; 621 clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 }; 627 628 flexcomm6: flexcomm@173000 { 629 compatible = "nxp,lp-flexcomm"; 630 reg = <0x173000 0x1000>; 631 interrupts = <35 0>; 632 status = "disabled"; 633 634 /* Empty ranges property implies parent and child address space is identical */ 635 ranges = <>; 636 #address-cells = <1>; 637 #size-cells = <1>; 638 639 flexcomm6_lpuart6: uart@173000 { 640 compatible = "nxp,lpuart"; 641 reg = <0x173000 0x1000>; 642 clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; 643 status = "disabled"; 644 }; 645 646 flexcomm6_lpspi6: spi@173000 { 647 compatible = "nxp,lpspi"; 648 reg = <0x173000 0x1000>; 649 clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 tx-fifo-size = <8>; 653 rx-fifo-size = <8>; 654 status = "disabled"; 655 }; 656 657 flexcomm6_lpi2c6: lpi2c@173800 { 658 compatible = "nxp,lpi2c"; 659 reg = <0x173800 0x1000>; 660 clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 }; 666 667 flexcomm7: flexcomm@174000 { 668 compatible = "nxp,lp-flexcomm"; 669 reg = <0x174000 0x1000>; 670 interrupts = <36 0>; 671 status = "disabled"; 672 673 /* Empty ranges property implies parent and child address space is identical */ 674 ranges = <>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 678 flexcomm7_lpuart7: uart@174000 { 679 compatible = "nxp,lpuart"; 680 reg = <0x174000 0x1000>; 681 clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; 682 status = "disabled"; 683 }; 684 685 flexcomm7_lpspi7: spi@174000 { 686 compatible = "nxp,lpspi"; 687 reg = <0x174000 0x1000>; 688 clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 tx-fifo-size = <8>; 692 rx-fifo-size = <8>; 693 status = "disabled"; 694 }; 695 696 flexcomm7_lpi2c7: lpi2c@174800 { 697 compatible = "nxp,lpi2c"; 698 reg = <0x174800 0x1000>; 699 clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 }; 705 706 flexcomm8: flexcomm@199000 { 707 compatible = "nxp,lp-flexcomm"; 708 reg = <0x199000 0x1000>; 709 interrupts = <47 0>; 710 status = "disabled"; 711 712 /* Empty ranges property implies parent and child address space is identical */ 713 ranges = <>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 717 flexcomm8_lpuart8: uart@199000 { 718 compatible = "nxp,lpuart"; 719 reg = <0x199000 0x1000>; 720 clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; 721 status = "disabled"; 722 }; 723 724 flexcomm8_lpspi8: spi@199000 { 725 compatible = "nxp,lpspi"; 726 reg = <0x199000 0x1000>; 727 clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 tx-fifo-size = <8>; 731 rx-fifo-size = <8>; 732 status = "disabled"; 733 }; 734 735 flexcomm8_lpi2c8: lpi2c@199800 { 736 compatible = "nxp,lpi2c"; 737 reg = <0x199800 0x1000>; 738 clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 status = "disabled"; 742 }; 743 }; 744 745 flexcomm9: flexcomm@19a000 { 746 compatible = "nxp,lp-flexcomm"; 747 reg = <0x19a000 0x1000>; 748 interrupts = <48 0>; 749 status = "disabled"; 750 751 /* Empty ranges property implies parent and child address space is identical */ 752 ranges = <>; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 756 flexcomm9_lpuart9: uart@19a000 { 757 compatible = "nxp,lpuart"; 758 reg = <0x19a000 0x1000>; 759 clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; 760 status = "disabled"; 761 }; 762 763 flexcomm9_lpspi9: spi@19a000 { 764 compatible = "nxp,lpspi"; 765 reg = <0x19a000 0x1000>; 766 clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 tx-fifo-size = <8>; 770 rx-fifo-size = <8>; 771 status = "disabled"; 772 }; 773 774 flexcomm9_lpi2c9: lpi2c@19a800 { 775 compatible = "nxp,lpi2c"; 776 reg = <0x19a800 0x1000>; 777 clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 }; 783 784 flexcomm10: flexcomm@19b000 { 785 compatible = "nxp,lp-flexcomm"; 786 reg = <0x19b000 0x1000>; 787 interrupts = <49 0>; 788 status = "disabled"; 789 790 /* Empty ranges property implies parent and child address space is identical */ 791 ranges = <>; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 795 flexcomm10_lpuart10: uart@19b000 { 796 compatible = "nxp,lpuart"; 797 reg = <0x19b000 0x1000>; 798 clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; 799 status = "disabled"; 800 }; 801 802 flexcomm10_lpspi10: spi@19b000 { 803 compatible = "nxp,lpspi"; 804 reg = <0x19b000 0x1000>; 805 clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 tx-fifo-size = <8>; 809 rx-fifo-size = <8>; 810 status = "disabled"; 811 }; 812 813 flexcomm10_lpi2c10: lpi2c@19b800 { 814 compatible = "nxp,lpi2c"; 815 reg = <0x19b800 0x1000>; 816 clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 }; 822 823 flexcomm11: flexcomm@19c000 { 824 compatible = "nxp,lp-flexcomm"; 825 reg = <0x19c000 0x1000>; 826 interrupts = <50 0>; 827 status = "disabled"; 828 829 /* Empty ranges property implies parent and child address space is identical */ 830 ranges = <>; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 834 flexcomm11_lpuart11: uart@19c000 { 835 compatible = "nxp,lpuart"; 836 reg = <0x19c000 0x1000>; 837 clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; 838 status = "disabled"; 839 }; 840 841 flexcomm11_lpspi11: spi@19c000 { 842 compatible = "nxp,lpspi"; 843 reg = <0x19c000 0x1000>; 844 clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 tx-fifo-size = <8>; 848 rx-fifo-size = <8>; 849 status = "disabled"; 850 }; 851 852 flexcomm11_lpi2c11: lpi2c@19c800 { 853 compatible = "nxp,lpi2c"; 854 reg = <0x19c800 0x1000>; 855 clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 status = "disabled"; 859 }; 860 }; 861 862 flexcomm12: flexcomm@19d000 { 863 compatible = "nxp,lp-flexcomm"; 864 reg = <0x19d000 0x1000>; 865 interrupts = <51 0>; 866 status = "disabled"; 867 868 /* Empty ranges property implies parent and child address space is identical */ 869 ranges = <>; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 873 flexcomm12_lpuart12: uart@19d000 { 874 compatible = "nxp,lpuart"; 875 reg = <0x19d000 0x1000>; 876 clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; 877 status = "disabled"; 878 }; 879 880 flexcomm12_lpspi12: spi@19d000 { 881 compatible = "nxp,lpspi"; 882 reg = <0x19d000 0x1000>; 883 clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 tx-fifo-size = <8>; 887 rx-fifo-size = <8>; 888 status = "disabled"; 889 }; 890 891 flexcomm12_lpi2c12: lpi2c@19d800 { 892 compatible = "nxp,lpi2c"; 893 reg = <0x19d800 0x1000>; 894 clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 status = "disabled"; 898 }; 899 }; 900 901 flexcomm13: flexcomm@19e000 { 902 compatible = "nxp,lp-flexcomm"; 903 reg = <0x19e000 0x1000>; 904 interrupts = <52 0>; 905 status = "disabled"; 906 907 /* Empty ranges property implies parent and child address space is identical */ 908 ranges = <>; 909 #address-cells = <1>; 910 #size-cells = <1>; 911 912 flexcomm13_lpuart13: uart@19e000 { 913 compatible = "nxp,lpuart"; 914 reg = <0x19e000 0x1000>; 915 clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; 916 status = "disabled"; 917 }; 918 919 flexcomm13_lpspi13: spi@19e000 { 920 compatible = "nxp,lpspi"; 921 reg = <0x19e000 0x1000>; 922 clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 tx-fifo-size = <8>; 926 rx-fifo-size = <8>; 927 status = "disabled"; 928 }; 929 930 flexcomm13_lpi2c13: lpi2c@19e800 { 931 compatible = "nxp,lpi2c"; 932 reg = <0x19e800 0x1000>; 933 clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 }; 938 }; 939 940 /* LPFlexcomm14/16 only support LPSPI function */ 941 lpspi14: spi@484000 { 942 compatible = "nxp,lpspi"; 943 reg = <0x484000 0x1000>; 944 interrupts = <13 0>; 945 clocks = <&clkctl4 MCUX_LPSPI14_CLK>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 tx-fifo-size = <8>; 949 rx-fifo-size = <8>; 950 status = "disabled"; 951 }; 952 953 954 /* LPFlexcomm15 only support LPI2C function. */ 955 lpi2c15: i2c@213000 { 956 compatible = "nxp,lpi2c"; 957 reg = <0x213000 0x1000>; 958 interrupts = <14 0>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&clkctl4 MCUX_LPI2C15_CLK>; 962 status = "disabled"; 963 }; 964 965 /* LPFlexcomm14/16 only support LPSPI function */ 966 lpspi16: spi@405000 { 967 compatible = "nxp,lpspi"; 968 reg = <0x405000 0x1000>; 969 interrupts = <53 0>; 970 clocks = <&clkctl4 MCUX_LPSPI16_CLK>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 tx-fifo-size = <8>; 974 rx-fifo-size = <8>; 975 status = "disabled"; 976 }; 977 978 usb0: usbd@418000 { 979 compatible = "nxp,ehci"; 980 reg = <0x418000 0x1000>; 981 interrupts = <40 0>; 982 interrupt-names = "usb_otg"; 983 clocks = <&usbclk>; 984 num-bidir-endpoints = <8>; 985 status = "disabled"; 986 }; 987 988 usb1: usbd@419000 { 989 compatible = "nxp,ehci"; 990 reg = <0x419000 0x1000>; 991 interrupts = <41 0>; 992 interrupt-names = "usb_otg"; 993 clocks = <&usbclk>; 994 num-bidir-endpoints = <8>; 995 status = "disabled"; 996 }; 997 998 usbphy: usbphy@414000 { 999 compatible = "nxp,usbphy"; 1000 reg = <0x414000 0x1000>; 1001 status = "disabled"; 1002 }; 1003 1004 mrt0: mrt@2d000 { 1005 compatible = "nxp,mrt"; 1006 reg = <0x2d000 0x100>; 1007 interrupts = <2 0>; 1008 num-channels = <4>; 1009 num-bits = <24>; 1010 clocks = <&clkctl2 MCUX_MRT_CLK>; 1011 resets = <&rstctl0 NXP_SYSCON_RESET(3, 26)>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 1015 mrt0_channel0: mrt_channel@0 { 1016 compatible = "nxp,mrt-channel"; 1017 reg = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 mrt0_channel1: mrt_channel@1 { 1022 compatible = "nxp,mrt-channel"; 1023 reg = <1>; 1024 status = "disabled"; 1025 }; 1026 1027 mrt0_channel2: mrt_channel@2 { 1028 compatible = "nxp,mrt-channel"; 1029 reg = <2>; 1030 status = "disabled"; 1031 }; 1032 1033 mrt0_channel3: mrt_channel@3 { 1034 compatible = "nxp,mrt-channel"; 1035 reg = <3>; 1036 status = "disabled"; 1037 }; 1038 }; 1039 1040 flexio: flexio@416000 { 1041 compatible = "nxp,flexio"; 1042 reg = <0x416000 0x1000>; 1043 status = "disabled"; 1044 interrupts = <55 0>; 1045 clocks = <&clkctl4 MCUX_FLEXIO0_CLK>; 1046 }; 1047 1048 os_timer_cpu0: timers@207000 { 1049 compatible = "nxp,os-timer"; 1050 reg = <0x207000 0x1000>; 1051 interrupts = <34 0>; 1052 status = "disabled"; 1053 }; 1054 1055 wwdt0: watchdog@e000 { 1056 compatible = "nxp,lpc-wwdt"; 1057 reg = <0xe000 0x1000>; 1058 interrupts = <42 0>; 1059 status = "disabled"; 1060 clk-divider = <1>; 1061 }; 1062 1063 wwdt1: watchdog@2e000 { 1064 compatible = "nxp,lpc-wwdt"; 1065 reg = <0x2e000 0x1000>; 1066 interrupts = <43 0>; 1067 status = "disabled"; 1068 clk-divider = <1>; 1069 }; 1070 1071 sc_timer: pwm@114000 { 1072 compatible = "nxp,sctimer-pwm"; 1073 reg = <0x114000 0x1000>; 1074 interrupts = <5 0>; 1075 status = "disabled"; 1076 clocks = <&clkctl0 MCUX_SCTIMER_CLK>; 1077 prescaler = <8>; 1078 #pwm-cells = <3>; 1079 }; 1080}; 1081 1082&systick { 1083 /* 1084 * RT700 cm33_cpu0 relies by default on the OS Timer for system 1085 * clock implementation, so the SysTick node is not to be enabled. 1086 */ 1087 status = "disabled"; 1088}; 1089 1090&xspi0 { 1091 compatible = "nxp,xspi"; 1092 status = "disabled"; 1093 interrupts = <42 0>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 clocks = <&clkctl0 MCUX_XSPI_CLK>; 1097}; 1098 1099&nvic { 1100 arm,num-irq-priority-bits = <3>; 1101}; 1102
